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Template Revision 272.7
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Note for Download Link of the Scroll ignore macro: |
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Table of Contents |
Overview
he The Trenz Electronic TEI0006 is an Industrial industrial grade module based on Intel® Cyclone 10 GX. Intel Intel® Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation of low cost FPGAs.
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Block Diagram
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add drawIO object here.
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0006 block diagram |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | false |
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| revision | 24 |
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| diagramName | TEI0006_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden | lbox | true |
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| diagramWidth | 638639 |
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| revision | 15 |
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Main Components
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0006 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | false |
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| revision | 8 |
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| diagramName | TEI0006_OV_MC |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| lbox | true |
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| diagramWidthdiagramWidth | 641 |
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| revision | 3 |
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 Image Modified
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- Intel® MAX 10, U18
- DC/DC convertor, U4...11
- SDRAM DDR3 Memory, U12 ...13- U13
- User LEDs, D1...4
- Ethernet TrancieverTransceiver, U2- U14
- SPI Flash Memory, U1 - U3
- Intel® Cyclone 10 GX, U23
- EEPROM, U64
- Buffer, U16
- 10-Channel Clock Multiplier, U14
- CryptoAuthentication Device (optional), U19
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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| Intel® MAX 10 | Programmed | See CPLD Firmware | Quad SPI Flash | Not Programmed |
| | EEPROM | Programmed | Ethernet MAC | | DDR3 SDRAM | Not Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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The TEI00006 TEI0006 module can be configured using different modes. Mode selection can be done using MSEL[2:0]. MSEL2 is potentially connected to GND so mode selection can be done using MSEL[1:0] which are connected to Bank 3 of Intel Max 10.
| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE Signal State | MSEL2 | MSEL1 | MSEL0 | Boot Mode |
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MSEL[2:0] | 0 | 1 | 0 | AS |
x4 x1 / Standard | | 0 | 0 | 0 | PS and FPP / Fast | | 0 | 0 | 1 | PS and FPP / Standard |
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By tying the CONF_DONE, nSTATUSNSTATUS, and nCONFIG NCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pinNSTATUS pin, it resets the chain by pulling its nSTATUS NSTATUS pin low.
| Scroll Title |
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| anchor | Table_OV_BP_CS |
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| title | Configuration signals. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signals | Connected to | Description | Note |
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| nCONFIGNCONFIG | 1.8V | Configuration trigger | From U18 ( Intel MAX 10Intel MAX 10) - Bank 3 | | CONF_DONE | 1.8V | Configuration done Configuration done | To U18 ( Intel MAX 10Intel MAX 10) - Bank 3 | | nSTATUSNSTATUS | 1.8V | Configuration status status | To U18 ( Intel MAX 10) Intel MAX 10) - Bank 3 | | DCLK | U1,U3 | Configuration clock clock | To U1 (Flash Memory) From U18 ( Intel MAX 10Intel MAX 10) - Bank 3 | | AS_DATA0...3 | U1 | Configuration data | To From U1 (Flash Memory) |
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | B2B | Connected to | Note |
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PERST | J2-99 | Bank A2 |
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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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Intel Cyclone 10 GX | Bank 1C | J3 |
24 Single ended () | 0.95V | GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P | Bank 1D | J3 |
24 Single ended () | 0.95V | GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P | Bank 2A | J2 |
1 2 Single ended | 1.8V | PERST, CLKUSR | Bank 2J | J2 | 46 Single ended (23 Diff pair) |
1.8VVCCIO2J |
| Bank 2K | J1 | 46 Single ended (23 Diff pair) | VCCIO2K |
| Bank 2L | J1 |
46 23 24 Diff pair) | VADJ up to 3 |
.0VV |
| Bank 3A | - | - | 1.35V | VDD_DDR | Bank 3B | - | - | 1.35V | VDD_DDR | Intel Max 10 | Bank 1A | J2 | 8 Single ended | 3.3V |
| Bank 1B | J2 | 5 Single ended | 3.3V |
| Bank 2 | J3 |
2 1 Single ended | 1.8VIO |
| Bank 3 | - | - | 1.8VIO |
| Bank 5 | J2 |
4 3 Single ended | 3.3V |
| Bank 6 | J2 | 2 Single ended | 3.3V |
| Bank 8 | J2 |
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JTAG Interface
JTAG access to the TEI0006 SoM is through B2B connector JM2J2. JTAGEN is pulled up to 3.3V and after power on, JTAG for MAX 10 CPLD is enabled. JTAG port of Cyclon 10 GX device is routed to MAX10 CPLD IOs. The default Firmware connects the JTAG port of the Cyclon 10 GX to the IO pins of the JTAG port in user IO mode. Setting JTAGEN to GND enables JTAG for the Cyclon 10 GX device.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector | Note |
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| TMS | J2-160 |
| | TDI | J2-159 |
| | TDO | J2-158 |
| | TCK | J2-157 |
JTAG_ENConnected
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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| Scroll Title |
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| anchor | Table_OBP_MIOs |
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| title | MIOs pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Connected to | B2B | Notes |
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| MAX_IO1...20, 22 | U18 (Intel MAX 10) - Bank 8 | J2 |
| | MAX_IO23..., 25, 26 | U18 (Intel MAX 10) - Bank 85
| J2 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | Designator | Notes |
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SPI DDR3 ...13 Tranciever- U14 |
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QSPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Schematic | Connected to | Notes |
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U1
| NCSO | CSS Bank (Configuration Bank) | Used when you are not configuring using AS | | DCK | DCLK | AS Configuration Clock | | AS_DATA0 | CSS Bank (Configuration Bank) | AS Configuration Pin |
| | AS_DATA1 | CSS Bank (Configuration Bank) |
| | AS Configuration DataAS_DATA2 | CSS Bank (Configuration Bank) | AS Configuration Data |
| | AS_DATA3 | CSS Bank (Configuration Bank) | AS Configuration Data |
| | U3 | QSPI_CS | Bank 2A |
| | QSPI_CK | Bank 2A |
| | QSPI_DATA0 | Bank 2A |
| | QSPI_DATA1 | Bank 2A |
| | QSPI_DATA2 | Bank 2A |
| | QSPI_DATA3 | Bank 2A |
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| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | U64 EEPROM Pin | B2B | U18 Intel Max 10 Pin | Notes |
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| I2C_SCL | SCL | J3-135 |
Connected to of Intel Max 10Connected to of Intel Max 10
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pins | I2C Address | Designator | Notes |
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| I2C_SCL, I2C_SDA | 0x53 | U64 |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0006 SoM has two 1 Gb GByte volatile DDR3 SDRAM IC for storing provided by Integrated Silicon Solution Inc for storing user application code and data.
- Part number: IS43TR16512BL
- Supply voltage: 1.35V35 V
- Speed: 800MHz: Half rate: 533 MHz; Quarter rate: max. 800 MHz
- Temperature: 0 ° C -40 °C to 95 ° C°C
Ethernet PHY
| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq Intel Cyclone 10 GX SoC connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signal Name | Connected to | B2B | Signal Description |
|---|
PHY1_MDI0_P PHY1_MDI0_N | - - | J2-93 J2-91 |
| PHY1_MDI1_P PHY1_MDI1_N | - - | J2-87 J2-85 |
| PHY1_MDI2_P PHY1_MDI2_N | - - | J2-81 J2-79 |
| PHY1_MDI3_P PHY1_MDI3_N | - - | J2-75 J2-73 |
| | ETH1_RST | U23, Bank 2A | - | Connected Pulled-up to DVDDH Voltage. | | ETH1_MDC | U23, Bank 2A | - | Connected Pulled-up to DVDDH Voltage. | | ETH1_MDIO | U23, Bank 2A | - | Connected Pulled-up to DVDDH Voltage. | | ETH1_TXD0...7 | U23, Bank 2A | - | 8 bit Transfer | | ETH1_RXD0...7 | U23, Bank 2A | -Recieve | 8 bit Receive | | ETH1_GTXCK | U23, Bank 2A | - |
| | ETH1_TXCLK | U23, Bank 2A | - |
| | ETH1_TXEN- | U23, Bank 2A | - |
| | ETH1_TXER- | U23, Bank 2A | - |
| | ETH1_RXCK | U23, Bank 2A | - | Connected to GNGPulled-down to GND. | | ETH1_RXDV | U23, Bank 2A | - | Connected to GNGPulled-down to GND. | | PHY1_INT | - | - | Connected Pulled-up to DVDDH Voltage. | | PHY1_LED1 | U18, Bank 2 | -J2 | Pulled-69Connected up to DVDDH Voltage. | | PHY1_LED2 | U18, Bank 2 | -J2 | Pulled-67Connected to GNGdown to GND. | | ETH1_CRS | U23, Bank 2A | - |
| | ETH1_XTAL_IN | ETH_CLKIN | - | From U21 (25MHz MEMS Oschillator25 MHz Oscillator) |
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Intel MAX 10
The TEI0006 is equipped with an Intel MAX 10 device an Intel MAX 10 device which is a single-chip, non-volatile low-cost programmable logic device (PLD) to integrate the optimal set of system components. Intel MAX 10 (U18) is power and configuration controller on TEI0006 SoM.
| Scroll Title |
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| anchor | Table_SIP_B2BMAX10 |
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| title | General PL I/O to B2B connectors Intel MAX 10 banks information |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
| Intel Max 10 Bank | Signals | Connected to | Description | Notes |
|---|
| Bank 1A | AIN0...7 | B2B- J2 |
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| | Bank 1B | TCK, TDO, TMS, TDI, JTAGEN | B2B- J2 |
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| | Bank 2 | PHY1_LED1 PHY1_LED2 | U23(Ethernet )PHY, U2U23( Ethernet )PHY, U2 | Ethernet LED Ethernet LED | Pulled-up to DVDDH. Pulled-down Tight to GNDTight to DVDDH. | | F_TCK, F_TDO, F_TDI, F_TMS | U23(Intel Cyclone 10 GX (U23) - Bank CSS | Intel Cyclone 10 JTAG signals |
| | I2C_SDA, I2C_SCL | EEPROM, U64(EEPROM)J3 ( B2B), J3 U14 (Programmable Oscillator), U14 | I2C EEPROM signals |
| | PLL_RST | U14 (Programmable Oscillator), U14 | Oscillator reset signal |
| | Bank 3 | nSTATUSNSTATUS, nCONFIGNCONFIG, CONF_DONE | U23(Intel Cyclone 10 GX (U23) - Bank CSS | Intel Cyclone 10 Configuration signals |
| | DCLK | U23(Intel Cyclone 10 GX (U23) - Bank CSS U1(SPI Flash), U1 | Intel Cyclone 10 Configuration clock from Flash memory |
| | MSEL0...1 | U23(Intel Cyclone 10 GX (U23) - Bank CSS | Intel Cyclone 10 Configuration mode signals |
| | DEV_CLRN, INIT_DONE | U23(Intel Cyclone 10 GX (U23) - Bank 2A |
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| | M10_IO0...4 | U23(Intel Cyclone 10 GX (U23) - Bank 2A |
|
| Bank 5
| DIS_GROUP1...4 | N-Channel MOSFET, T1...4 (N- Channel MOSFET) | Fast Discharching |
| | MAX_IO23...26 | B2B, J2 (B2B) | Intel MAX 10 GPIO |
| PG_0.95V, EN_0.95V PG_1.8VIO, EN_1.8VIO | U7(Voltage Regulator), U7U7( Voltage Regulator), U6 | Power control signals |
| Bank 6
| M10_CLK | U21(25MHz Oscillator)25 MHz Oscillator, U21 | Intel MAX 10 Clock |
| VADJ_VS0...2, VADJ_EN PG_1.35V, EN_1.35V PG_1.8V, EN_1.8V PG_VTT, EN_VTT PG_0V9, EN_0V9 | U11(Voltage Regulator), U11U8( Voltage Regulator), U8U5( Voltage Regulator), U5U9( Voltage Regulator), U9U4( Voltage Regulator), U4 | Power control signals |
| | PHY1_33LED1...2 | B2B, J2 (B2B) | Ethernet LED |
| LED_FP_1 LED_FP_2...4 | D1 D2...4 | User LEDs | Red LED Green LED | | Bank 8 | M10_nSTATUS, M10_nCONFIG, M10_CONF_DONE | B2B, J2J2(B2B) | Intel MAX 10 configuration signals |
| | MAX_IO1...20, 22 | B2B, J2(B2B) | Intel MAX 10 GPIO |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Color | Connected to | Active Level | Note |
|---|
| D1 | Red | LED_FP_1 | Active high |
| | D2 | Green | LED_FP_2 | Active high |
| | D3 | Green | LED_FP_3 | Active high |
| | D4 | Green | LED_FP_4 | Active high |
|
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Clock Sources
The TEI0006 has one crystal, three MEMS oscillator oscillators and a programmable clock generator.
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Description | Frequency |
|---|
NoteU14 | | Connected to |
|---|
| U21 | MEMS Oscillator | 25MHz | U2 Ethernet | | U15 | MEMS Oscillator | 25MHz | IN0 of U14 | | U17 | MEMS Oscillator |
48MHz | | 100 MHz | U23, BANK2A USRCLK | | Y1 | Crystal Oscillator | 50MHz | crystal input of U14 | | U14 |
| Programmable Oscillator | Variable | - |
|
| Scroll Title |
|---|
| anchor | Table_OBP_CLK_PO |
|---|
| title | Programmable Oscillator connections |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Signals | Clock Type | In/ Out | Connected to | Frequency | Note |
|---|
IN1IN1IN0_N | Differential | In In | Oscillator, U15 |
(Oscillator)IN1..3
| | IN3 | Differential | In | B2B, J3 |
(B2B), XB | Differential |
| Oscillator, Y1 | 50 MHz |
| CLK0 |
XBU17 (Oscillator) GND | 48 MHz | | Out | Intel Cyclone 10 GX (U23)- Bank 2A | User | Default off | CLK1 |
CLK0J3(B2B) | 25MHz| B2B, J3 | User | Default off | | REFCLK_EMIFP | Differential | Out | Intel Cyclon 10 GX (U23)- |
VariableU23 (| Intel Cyclon 10 GX (U23)- Bank 1D | User |
Variable| Default off | | CLK8...9 | Differential | Out |
U23 (| Intel Cyclon 10 GX (U23)- Bank 1C |
Variable | |
Power and Power-On Sequence
...
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
| Note |
|---|
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
CryptoAuthentication
ATECC608A (U19) is a CryptoAuthentication device connected to the I2C bus. This chip is optional, for further description see datasheet of manufacturer.
| Scroll Title |
|---|
| anchor | Table_OBP_EEP |
|---|
| title | I2C Interface of CryptoAuthentication |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | U19 Pin | B2B | U18 Intel Max 10 Pin | Notes |
|---|
| I2C_SCL | SCL | J3-135 | Bank 2 - K2 | - | | I2C_SDA | SDA | J3-137 | Bank 2 - L2 | - |
|
Power and Power-On Sequence
| Page properties |
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|
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
Power supply with minimum current capability of 1 A for system startup is recommended.
Power Consumption
| Scroll Title |
|---|
| anchor | Table_PWR_PC |
|---|
| title | Power Consumption |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA | Typical Current |
|---|
| Intel Cyclone 10 GX | TBD* | | Intel MAX 10 | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
...
| anchor | Table_PWR_PC |
|---|
| title | Power Consumption |
|---|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
...
* TBD - To Be Determined
Power Distribution Dependencies
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Only |
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 Image Removed
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Power-On Sequence
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| Scroll Title |
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| anchor | Figure_PWR_PSPD |
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| title | Power SequencyDistribution |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox |
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true5| 11 | | diagramName | TEI0006_PWR_ |
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|
PS| PD | | simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 639 |
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| Scroll Only |
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 Image Removed
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Image Added |
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Power-On Sequence
Voltage regulators can be enabled through U18 (Intel MAX 10) - Bank 5 and 6.
| Scroll Title |
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| anchor | TableFigure_PWR_PRPS |
|---|
| title | Module power rails.Power Sequence |
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|
tablelayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultsortByColumn1sortEnabledcellHighlightingtrue |
| Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Voltage Level | Direction | Notes |
|---|
VCCIO2K | 53, 54 | - | - | 1.8 V | Input | VADJ | 140,142 | - | - | 3.0 V | Output | VCCIO2J | - | 29,30 | 1.8 V | Input | 3.3V | - | 149,150 | - | 3.3 V | Output | 1.8_VIO | - | - | 139 | 1.8 V | Output |
Bank Voltages
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| anchor | Table_PWR_BV |
|---|
| title | Zynq SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
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Bank 1D
...
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| diagramName | TEI0006_PWR_PS |
|---|
| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 639 |
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| Scroll Only |
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Image Added |
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Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | B2B Connector J1 Pin | B2B Connector J2 Pin | B2B Connector J3 Pin | Voltage Level | Direction | Notes |
|---|
| VIN | 145, 147,149, 151, 153, 155, 157, 159 | - | - | 5 V | Input |
| | VCCIO2K | 53, 54 | - | - | 1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 V | Input |
| | VADJ | 140,142 | - | - | adjustable between 1.8 V - 3.0 V | Output | Voltages according to EP53A8HQI datasheet but restricted to allowed bank voltage | | VCCIO2J | - | 29,30 | - | 1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 V | Input |
| 3.3V | - | 149,150 | - | 3.3 V | Output |
| | 1.8_VIO | - | - | 139 | 1.8 V | Output |
|
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
|---|
| title | SoC bank voltages. |
|---|
|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
| FPGA | FPGA Bank | Voltage Level | Notes |
|---|
| Intel Cyclone 10 GX | Bank 1C | 0.95 V |
| Bank 1D | 0.95 V |
| | Bank 2A | 1.8 V | 1.8VIO | | Bank 2J | 1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 V | VCCIO2J | | Bank 2K | 1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 V | VCCIO2K | | Bank 2L | adjustable between 1.8 V - 3.0 V | Voltages according to EP53A8HQI datasheet | | Bank 3A | 1.35 V | VDD_DDR | | Bank 3B | 1.35 V | VDD_DDR | | Intel Max 10 | Bank 1A | 3.3 V |
| | Bank 1B | 3.3 V |
| | Bank 2 | 1.8 V | 1.8VIO | | Bank 3 | 1.8 V | 1.8VIO | | Bank 5 | 3.3V |
| | Bank 6 | 3.3V |
| | Bank 8 | 3.3V |
|
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Board to Board Connectors
| Page properties |
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|
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
| Include Page |
|---|
| 6 x 6 SoM LSHM B2B Connectors |
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| 6 x 6 SoM LSHM B2B Connectors |
|---|
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|
| Include Page |
|---|
| 6 x 8 SoM SS5/ST5 B2B Connectors |
|---|
| 6 x 8 SoM SS5/ST5 B2B Connectors |
|---|
|
Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
|---|
| anchor | Table_TS_AMR |
|---|
| title | Absolute maximum ratings |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
| Symbols | Description | Min | Max | Unit | Note |
|---|
| VIN | Power supply | -0.3 | 6.0 | V | Detemined by U10. | | VCCIO - 3 V I/O | I/O buffers power supply | -0.5 | 4.10 | V | Intel Cyclone 10 GX | | VCCIO - LVDS I/O | I/O buffers power supply | -0.5 | 2.46 | V | Intel Cyclone 10 GX | | VADJ | Adjustable voltage | -0.5 | 4.10 | V | Intel Cyclone 10 GX | | T_STG | Storage temperature | -40 | 85 | °C |
|
|
use "include page" macro and link to the general B2B connector page of the module series,
...
TEI0006 module has three Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.
- 3x REF-192552-02 (160-pins, 80 pins per row)
- ST5 Mates with SS5
Operating Temperature: -55°C ~ 125°C
Current Rating: 1.6 A per ContactNumber of Positions: ??
...
Technical Specifications
Absolute Maximum Ratings
...
| anchor | Table_TS_AMR |
|---|
| title | PS absolute maximum ratings |
|---|
| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
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Recommended Operating Conditions
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| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
|---|
|
UnitsVCC87.93| See Intel Cyclone 10 GX datasheet. | VCCP | 0.87 | 0.93See Intel | See Intel Cyclone 10 GX datasheet. |
VCCERAM087093See Intel Cyclone 10 GX datasheet. | | VCCPT | 1.71 | 1.89 | V | See Intel Cyclone 10 GX datasheet. | | VCCPGM | 1.71 | 1.89 | V | See Intel Cyclone 10 GX datasheet. | | VCCIO | 2.85 | 3.15 | V | See Intel Cyclone 10 GX datasheet. | | VCCA_PLL | 1.71 | 1.89 | V | See Intel Cyclone 10 GX datasheet. | | T_J | 0 | 85 | °C | See Intel Cyclone 10 GX datasheet. | |
Physical Dimensions
Module size: 80 mm × 60 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
- PCB thickness: 1.65 mm
Physical Dimensions
Module size: 60 mm × 80 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
- PCB thickness: 1.7 mm
| Page properties |
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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | false |
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| revision | 3 |
|---|
| diagramName | TEI0006_TS_PD |
|---|
| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 611 |
|---|
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| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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|  Image Added
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Currently Offered Variants
| Page properties |
|---|
|
Set correct link to the shop page overview table of the product on English and German. Example for TE0728: ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ DEU Page: https://shop |
| Page properties |
|---|
|
In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadminde/docsProdukte/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF | Note |
|---|
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ if not available, set. |
| Scroll Title |
|---|
| anchor | FigureTable_TSVCP_PDSO |
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| title | Physical DimensionTrenz Electronic Shop Overview |
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|
| ignoredrawioborderfalseviewerToolbartruefitWindowfalsediagramDisplayNamelboxtruerevision2 |
| diagramName | TEI0006_TS_PD |
|---|
| simpleViewer | false |
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width | | links | auto |
|---|
| tbstyle | hidden |
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| diagramWidth | 641 |
|---|
| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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|
Image Removed |
Currently Offered Variants
...
Set correct link to the shop page overview table of the product on English and German.
Example for TE0728:
ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/
DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/
if not available, set.
Revision History
Hardware Revision History
| Scroll Title |
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| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
|---|
|
| Date | Revision | Changes | Documentation Link |
|---|
| 202-12-23 | 03 | - two input cloock signals on B2B connected directly to GXBL1C bank
| REV03 | | 2019-09-11 | 02 | - added 100MHz MEMS oscillator, remove CLKUSR signal from J2
- replaced U21/U15 by SiT8008
- added pull-up to M10_NSTATUS signal
- added pull-up to M10_DEVCLRN, removed signal from J2
- added optional CryptoAuthentication chip U19
| REV02 | | 2018-08-10 | 01 | - | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
...
https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/
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| Scroll Title |
|---|
| anchor | TableFigure_VCPRV_SOHRN |
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| title | Trenz Electronic Shop Overview Board hardware revision number. |
|---|
|
tablelayoutorientationportraitsortDirectionASCrepeatTableHeaders |
| sortByColumn | 1 |
|---|
sortEnabled | default | | cellHighlighting | true |
|---|
| Trenz shop TE0728 overview page |
|---|
| English page | German page |
Revision History
Hardware Revision History
| diagramDisplayName | |
|---|
| lbox | false |
|---|
| revision | 3 |
|---|
| diagramName | TEI0006_RV_RHN |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | top |
|---|
| diagramWidth | 178 |
|---|
|
|
| Scroll Only |
|---|
| scroll-pdf | true |
|---|
| scroll-office | true |
|---|
| scroll-chm | true |
|---|
| scroll-docbook | true |
|---|
| scroll-eclipsehelp | true |
|---|
| scroll-epub | true |
|---|
| scroll-html | true |
|---|
|  Image Added
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| Scroll Title |
|---|
| anchor | Table_RH_HRH |
|---|
| title | Hardware Revision History |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| Date | Revision | Changes |
|---|
2018-07-27 | 01 | -
Document Change History
| Page properties |
|---|
|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
...
| Scroll Title |
|---|
| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
|---|
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| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
|
| | Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Modified date | | dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
| Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| - corrected Bank Voltages for Bank 2J (VCCIO2J) and Bank 2K (VCCIO2K)
| | 2022-03-18 | v.85 | Vitali Tsiukala | - Added Info about Gigabit Transceivers
| | 2021-06-07 | | Martin Rohrmüller | - corrected Physical Dimension figure
- updated to REV03
| | v.82 | Martin Rohrmüller | | 2019-06-14 | v.80 | Pedram Babakhani | Figures updated - Technical specifications updated
| | v.69 | Pedram Babakhani | | change list | -- | all | | Page info |
|---|
| infoType | Modified users |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| |
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