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Template Revision 272.7

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

...

The Trenz Electronic TEI0006 is an Industrial industrial grade module based on Intel® Cyclone 10 GX. Intel  Intel® Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation of low cost FPGAs.

...

  • Intel® Cyclone 10 GX Industrial [10CX220YF780I5G]
    • Package: FBGA-780
    • Speed Grade: 5 (Fastest)
    • Temperature: -40°C ~ to 100°C
    • Package compatible device 10CX150 and 10CX105 as assembly variant on request possible
  • 2x SDRAM DDR3L Memory IC 8Gb, 800MHz 8 Gbit (1 GByte), Half rate: 533 MHz; Quarter rate: max. 800 MHz
  • 2x SPI Flash, 1 Gb
  • 2x Transceiver Full Ethernet 64-QFN 
  • Programmable Oscillator
  • Gbit (128 MByte)
  • 1x Gigabit Ethernet
  • 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/Clock Multiplier
  • Intel® MAX 10 as System Controller (CPLD)
  • 2Kb 2 Kbit EEPROM Memory

  • 4x User LED 

  • I/O interfaces: 226/94/46 (IOs/DIFF. Pairs/LVDS Pairs)
  • 12 x 12.5Gbps Transceiver
  • 284 GPIO
  • 118 LVDS
    • 12 XCVR

  • Board to Board (B2B) Connection: Plug-on module with 3 x 160-pin Samtec Razor Beam (ST5) connectors

  • 5 V Power Supply:

    5V

  • Dimension: 80m x 60m

Block Diagram

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Scroll Title
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titleTEI0006 block diagram


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Main Components

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Scroll Title
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titleTEI0006 main components


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  1. Intel® MAX 10, U18
  2. DC/DC convertor, U4...11
  3. SDRAM DDR3 Memory, U12 ...13- U13
  4. User LEDs, D1...4
  5. Ethernet TrancieverTransceiver, U2- U14
  6. SPI Flash Memory, U1 - U3
  7. Intel® Cyclone 10 GX, U23
  8. EEPROM, U64
  9. Buffer, U16
  10. 10-Channel Clock Multiplier, U14
  11. CryptoAuthentication Device (optional), U19

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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Scroll Title
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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Intel® MAX 10ProgrammedSee CPLD Firmware

Quad SPI Flash

Not Programmed


EEPROMProgrammed

Programmable Oscillator configurationEthernet MAC

DDR3 SDRAMNot Programmed



Configuration Signals

...

The TEI0006 module can be configured using different modes. Mode selection can be done using MSEL[2:0]. MSEL2 is potentially connected to GND so mode selection can be done using MSEL[1:0] which are connected to Bank 3 of Intel Max 10.

Scroll Title
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titleBoot process.

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MODE Signal State

MSEL2MSEL1MSEL0Boot Mode

MSEL[2:0]

010

AS x4 / Fast

011

AS x1 / Standard

000PS and FPP / Fast
001PS and FPP / Standard


By tying the CONF_DONE, nSTATUSNSTATUS, and nCONFIG NCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pinNSTATUS pin, it resets the chain by pulling its nSTATUS NSTATUS pin low.

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titleConfiguration signals.

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SignalsConnected toDescriptionNote
nCONFIGNCONFIG1.8VConfiguration triggerFrom U18 ( Intel MAX 10Intel MAX 10) - Bank 3
CONF_DONE1.8VConfiguration done To U18 ( Intel MAX 10Intel MAX 10) - Bank 3
nSTATUSNSTATUS1.8VConfiguration status To U18 ( Intel MAX 10Intel MAX 10) - Bank 3
DCLKU1,U3Configuration clock 

To U1 (Flash Memory)

From U18 ( Intel MAX 10Intel MAX 10) - Bank 3

AS_DATA0...3U1Configuration dataFrom U1 (Flash Memory)


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Scroll Title
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titleGeneral PL I/O to B2B connectors information

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FPGAFPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes

Intel Cyclone 10 GX

Bank 1C

J3

24 Single ended (

12 Diff pair

)

0.95V

GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P

Bank 1D

J3

24 Single ended (

12 Diff pair

)

0.95V

GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P

Bank 2A

J2

2 Single ended

1.8V

PERST, CLKUSR

Bank 2J

J2

46 Single ended (23 Diff pair)

1.8V

VCCIO2J


Bank 2K

J1

46 Single ended (23 Diff pair)

VCCIO2K


Bank 2L

J1

46

48 Single ended (

23

24 Diff pair)

VADJ up to 3

.0V

V


Bank 3A

-

-

1.35V

VDD_DDR

Bank 3B

-

-

1.35V

VDD_DDR

Intel Max 10

Bank 1A

J2

8 Single ended

3.3V


Bank 1B

J2

5 Single ended

3.3V


Bank 2

J3

2

1 Single ended

1.8VIO


Bank 3

-

-

1.8VIO


Bank 5

J2

4

3 Single ended

3.3V


Bank 6

J2

2 Single ended

3.3V


Bank 8

J2

25

23 Single ended

3.3V




JTAG Interface

JTAG access to the TEI0006 SoM is through B2B connector JM2J2. JTAGEN is connected pulled up to 3.3V and after power on JTAG will be enabled., JTAG for MAX 10 CPLD is enabled. JTAG port of Cyclon 10 GX device is routed to MAX10 CPLD IOs. The default Firmware connects the JTAG port of the Cyclon 10 GX to the IO pins of the JTAG port in user IO mode. Setting JTAGEN to GND enables JTAG for the Cyclon 10 GX device.

Scroll Title
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titleJTAG pins
Scroll Title
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titleJTAG pins connection

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JTAG Signal

B2B Connector

Note
TMSJ2-160
TDIJ2-159
TDOJ2-158
TCK

J2-157


JTAGENJ2-105Connected Pulled up to 3.3V.


MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



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titleMIOs pins

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MIO PinConnected toB2BNotes
MAX_IO1...20, 22U18 (Intel MAX 10) - Bank 8J2
MAX_IO23..., 25, 26U18 (Intel MAX 10) - Bank 85
J2



On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

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titleOn board peripherals

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Chip/InterfaceDesignatorNotes

QSPI Flash Memory

U1 - U3U1- AS configuration
EEPROMU64
DDR3 SDRAM MemoryU12 ...13- U13
Ethernet PHYU2- U14

Intel Max 10U18System controller

User LEDs

D1...4D1 (Red), D2...4 (Green)
OscillatorsU14, U15, U17, U21, Y1

CryptoAuthentication DeviceU19optional


QSPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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Scroll Title
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titleQuad SPI interface MIOs and pins

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AS Configuration Data
DesignatorSchematicConnected toNotes
U1



NCSOCSS Bank (Configuration Bank)Used when you are not configuring using AS
DCKDCLKAS Configuration Clock
AS_DATA0CSS Bank (Configuration Bank)
AS Configuration PinAS_DATA1CSS Bank (Configuration Bank)
AS_DATA2CSS Bank (Configuration Bank)
AS Configuration DataAS_DATA3CSS Bank (Configuration Bank)AS Configuration Data
U3QSPI_CSBank 2A
QSPI_CKBank 2A
QSPI_DATA0Bank 2A
QSPI_DATA1Bank 2A
QSPI_DATA2Bank 2A
QSPI_DATA3Bank 2A


...

Scroll Title
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titleI2C EEPROM interface MIOs and pins

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Schematic

U64 EEPROM Pin

B2B

U18 Intel Max 10 Pin

Notes
I2C_SCLSCLJ3-135
Connected to Intel Max 10 (U18)-
Bank 2 - K2
I2C_SDASDAJ3-137
Connected to Intel Max 10 (U18)-
Bank 2 - L2



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titleI2C address for EEPROM

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PinsI2C AddressDesignatorNotes
I2C_SCL, I2C_SDA0x53U64


...

The TEI0006 SoM has two 1 Gb GByte volatile DDR3 SDRAM IC provided by Integrated Silicon Solution Inc for storing user application code and data.

  • Part number: IS43TR16512BL
  • Supply voltage: 1.35V35 V
  • Speed: 800MHz: Half rate: 533 MHz; Quarter rate: max. 800 MHz
  • Temperature:  0 ° C -40 °C to 95 ° C°C

Ethernet PHY

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titleEthernet PHY to Intel Cyclone 10 GX SoC connections

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Signal NameConnected toB2BSignal Description

PHY1_MDI0_P

PHY1_MDI0_N

-

-

J2-93

J2-91


PHY1_MDI1_P

PHY1_MDI1_N

-

-

J2-87

J2-85


PHY1_MDI2_P

PHY1_MDI2_N

-

-

J2-81

J2-79


PHY1_MDI3_P

PHY1_MDI3_N

-

-

J2-75

J2-73


ETH1_RSTU23, Bank 2A-Connected Pulled-up to DVDDH Voltage.
ETH1_MDCU23, Bank 2A-Connected Pulled-up to DVDDH Voltage.
ETH1_MDIOU23, Bank 2A-Connected Pulled-up to DVDDH Voltage.
ETH1_TXD0...7U23, Bank 2A-8bit 8 bit Transfer
ETH1_RXD0...7U23, Bank 2A-8bit Recieve8 bit Receive
ETH1_GTXCKU23, Bank 2A-
ETH1_TXCLKU23, Bank 2A-
ETH1_TXENU23, Bank 2A-
ETH1_TXERU23, Bank 2A-
ETH1_RXCKU23, Bank 2A-Connected to GNGPulled-down to GND.
ETH1_RXDVU23, Bank 2A-Connected to GNGPulled-down to GND.
PHY1_INT--Connected Pulled-up to DVDDH Voltage.
PHY1_LED1U18, Bank 2

-J2

Pulled-69Connected up to DVDDH Voltage.
PHY1_LED2U18, Bank 2-J2Pulled-67Connected to GNGdown to GND.
ETH1_CRSU23, Bank 2A-
ETH1_XTAL_INETH_CLKIN-From U21 (25MHz MEMS Oschillator25 MHz Oscillator)


Intel MAX 10

The TEI0006 is equipped with an Intel MAX 10 device which is a single-chip, non-volatile low-cost programmable logic device (PLD) to integrate the optimal set of system components. Intel MAX 10 (U18) is power and configuration controller on TEI0006 SoM. 

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titleIntel MAX 10 banks information

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Intel Max 10 BankSignalsConnected to DescriptionNotes
Bank 1AAIN0...7B2B- J2

Bank 1BTCK, TDO, TMS, TDI, JTAGENB2B- J2

Bank 2

PHY1_LED1

PHY1_LED2

Ethernet PHY, U23U2

Ethernet PHY, U23U2

Ethernet LED

Ethernet LED

Pulled-up to DVDDH.

Pulled-down Tight to GND.

Tight to DVDDH

F_TCK, F_TDO, F_TDI, F_TMSIntel Cyclone 10 GX (U23) - Bank CSSIntel Cyclone 10 JTAG signals
I2C_SDA, I2C_SCL

EEPROM, U64

B2B, J3 

Programmable Oscillator, U14

I2C EEPROM signals
PLL_RST

Programmable Oscillator, U14

Oscillator reset signal
Bank 3nSTATUSNSTATUS, nCONFIGNCONFIG, CONF_DONEIntel Cyclone 10 GX (U23) - Bank CSSIntel Cyclone 10 Configuration signals
DCLK

Intel Cyclone 10 GX (U23) - Bank CSS

SPI Flash, U1

Intel Cyclone 10

Configuration clock from Flash memory


MSEL0...1Intel Cyclone 10 GX (U23) - Bank CSS

Intel Cyclone 10

Configuration mode signals


DEV_CLRN, INIT_DONEIntel Cyclone 10 GX (U23) - Bank 2A

M10_IO0...4Intel Cyclone 10 GX (U23) - Bank 2A

Bank 5

DIS_GROUP1...4N-Channel MOSFET, T1...4Fast Discharching
MAX_IO23...26B2B, J2Intel MAX 10 GPIO

PG_0.95V, EN_0.95V

PG_1.8VIO, EN_1.8VIO

Voltage Regulator, U7

Voltage Regulator, U7U6

Power control signals
Bank 6




M10_CLK25MHz 25 MHz Oscillator, U2U21Intel MAX 10 Clock

VADJ_VS0...2, VADJ_EN

PG_1.35V, EN_1.35V

PG_1.8V, EN_1.8V

PG_VTT, EN_VTT

PG_0V9, EN_0V9

Voltage Regulator, U11

Voltage Regulator, U8

Voltage Regulator, U5

Voltage Regulator, U9

Voltage Regulator, U4

Power control signals
PHY1_33LED1...2

B2B, J2

Ethernet LED

LED_FP_1

LED_FP_2...4

D1

D2...4

User LEDs

Red LED

Green LED

Bank 8

M10_nSTATUS, M10_nCONFIG, M10_CONF_DONE

B2B, J2Intel MAX 10 configuration signals
MAX_IO1...20, 22B2B, J2Intel MAX 10 GPIO


...

Clock Sources

The TEI0006 has one crystal, three MEMS oscillator oscillators and a programmable clock generator. 

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titleOsillators

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DesignatorDescriptionFrequency
Note
Connected to
U21MEMS Oscillator25MHzU2 Ethernet
U15MEMS Oscillator25MHzIN0 of U14
U17MEMS Oscillator100 MHzU23, BANK2A USRCLK
Y1Crystal Oscillator
48MHz
50MHzcrystal input of U14
U14Programmable OscillatorVariable-



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titleProgrammable Oscillator connections

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25MHzVariable
SignalsClock TypeIn/ OutConnected toFrequencyNote

IN1IN0_P

IN1IN0_N

Differential

In

In

Oscillator, U15

GND

25 MHz
IN1..3 IN3 DifferentialInB2B, J3Variable

XA, XB

Differential

Oscillator, U17Y1

GND

48 50 MHz

CLK0

DifferentialOutIntel Cyclone 10 GX (U23)- Bank 2AUserDefault off

CLK1...4

DifferentialOutB2B, J3UserDefault off
REFCLK_EMIFPDifferentialOutIntel Cyclon 10 GX (U23)- Bank 3BUserDefault off
CLK6...7DifferentialOutIntel Cyclon 10 GX (U23)- Bank 1DUserVariableDefault off
CLK8...9DifferentialOutIntel Cyclon 10 GX (U23)- Bank 1CVariable

Power and Power-On Sequence

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hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

UserDefault off


CryptoAuthentication

ATECC608A (U19) is a CryptoAuthentication device connected to the I2C bus. This chip is optional, for further description see datasheet of manufacturer.

Power Supply

Power supply with minimum current capability of 1 A for system startup is recommended.

...

Scroll Title
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titlePower ConsumptionI2C Interface of CryptoAuthentication

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Schematic
FPGA

U19 Pin

Typical Current
B2B

U18 Intel

Cyclone

Max 10

GX

Pin

TBD*
Intel MAX 10TBD*

* TBD - To Be Determined

Power Distribution Dependencies

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anchorFigure_PWR_PD
titlePower Distribution

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Power-On Sequence

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Notes
I2C_SCLSCLJ3-135Bank 2 - K2-
I2C_SDASDAJ3-137Bank 2 - L2-


Power and Power-On Sequence

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hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 1 A for system startup is recommended.

Power Consumption

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titlePower Consumption

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FPGATypical Current
Intel Cyclone 10 GXTBD*
Intel MAX 10TBD*


* TBD - To Be Determined

Power Distribution Dependencies

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titlePower SequenceDistribution


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Power

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-On Sequence

Voltage regulators can be enabled through U18 (Intel MAX 10) - Bank 5 and 6.

title
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titleModule power rails.Power Sequence


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9
Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

Voltage LevelDirectionNotes
VCCIO2K53, 54--1.8 VInputVADJ140,142--3.0 VOutputVCCIO2J-29,301.8 VInput

3.3V

-149,150-3.3 VOutput1.8_VIO--1391.8 VOutput

Bank Voltages

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titleSoC bank voltages.

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Bank 1D

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Power Rails

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titleModule power rails.

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Power Rail Name

B2B Connector

J1 Pin

B2B Connector

J2 Pin

B2B Connector

J3 Pin

Voltage LevelDirectionNotes
VIN145, 147,149, 151, 153, 155, 157, 159--5 VInput
VCCIO2K53, 54--1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 VInput
VADJ140,142--adjustable between 1.8 V - 3.0 VOutputVoltages according to EP53A8HQI datasheet but restricted to allowed bank voltage
VCCIO2J-29,30-1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 VInput

3.3V

-149,150-3.3 VOutput
1.8_VIO--1391.8 VOutput


Bank Voltages

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titleSoC bank voltages.

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FPGAFPGA BankVoltage LevelNotes
Intel Cyclone 10 GXBank 1C0.95 V

Bank 1D

0.95 V
Bank 2A1.8 V1.8VIO
Bank 2J1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 VVCCIO2J
Bank 2K1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 VVCCIO2K
Bank 2Ladjustable between 1.8 V - 3.0 VVoltages according to EP53A8HQI datasheet
Bank 3A1.35 VVDD_DDR
Bank 3B1.35 VVDD_DDR
Intel Max 10Bank 1A3.3 V
Bank 1B3.3 V
Bank 21.8 V1.8VIO
Bank 31.8 V1.8VIO
Bank 53.3V
Bank 63.3V
Bank 83.3V



Board to Board Connectors

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  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    6 x 6 SoM LSHM B2B Connectors
    6 x 6 SoM LSHM B2B Connectors

Include Page
6 x 8 SoM SS5/ST5 B2B Connectors
6 x 8 SoM SS5/ST5 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

use "include page" macro and link to the general B2B connector page of the module series,

...

TEI0006 module has three Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.

  • 3x REF-192552-02 (160-pins, 80 pins per row) 
  • ST5 Mates with SS5

Operating Temperature: -55°C ~ 125°C
Current Rating: 1.6 A per ContactNumber of Positions: ??

...

Technical Specifications

Absolute Maximum Ratings

...

anchorTable_TS_AMR
titleAbsolute maximum ratings

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3 V I/O

Intel Cyclone 10 GX

...

Recommended Operating Conditions

...

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titleRecommended operating conditions.Absolute maximum ratings

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Symbols
Parameter
DescriptionMinMaxUnitNote
VINPower supply-0.36.0VDetemined by U10.
VCCIO - 3 V I/OI/O buffers power supply-0.54.10V

Intel Cyclone 10 GX

VCCIO - LVDS I/OI/O buffers power supply-0.52.46V

Intel Cyclone 10 GX

VADJAdjustable voltage-0.54.10V

Intel Cyclone 10 GX

T_STGStorage temperature-4085°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

See Intel MAX 10 datasheet.
Scroll Title
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titleRecommended operating conditions.

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ParameterMinMaxUnitReference Document
VIN5.05.0V
VCCIO2.853.15VSee Intel Cyclone 10 GX datasheet.
VADJ2.853.15VVCCIO
UnitsReference Document
VCC0.870.93VSee Intel Cyclone 10 GX datasheet.
VCCP0.870.93VSee Intel Cyclone 10 GX datasheet.
VCCERAM0.870.93VSee Intel Cyclone 10 GX datasheet.
VCCPT1.711.89VSee Intel Cyclone 10 GX datasheet.
VCCPGM1.711.89VSee Intel Cyclone 10 GX datasheet.
VCCIO2.853.15VSee Intel Cyclone 10 GX datasheet.
VCCA_PLL1.711.89VSee Intel Cyclone 10 GX datasheet.
VCCH_GXB1.711.89VSee Intel MAX 10 datasheet.
VCC_ONE3.1353.465VSee Intel MAX 10 datasheet.
VCCA3.1353.465VSee Intel MAX 10 datasheet.
VCCIO3.135 / 1.713.465 / 1.89VSee Intel MAX 10 datasheet.
T_OP085°C


Physical Dimensions

  • Module size: 60 mm × 80 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

  • PCB thickness: 1.6 7 mm
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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


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titlePhysical Dimension


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titleHardware Revision History

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Documentation Link
DateRevisionChangesDocumentation Link
202-12-2303
  • two input cloock signals on B2B connected directly to GXBL1C bank
REV03
2019-09-1102
  • added 100MHz MEMS oscillator, remove CLKUSR signal from J2
  • replaced U21/U15 by SiT8008
  • added pull-up to M10_NSTATUS signal
  • added pull-up to M10_DEVCLRN, removed signal from J2
  • added optional CryptoAuthentication chip U19
REV02DateRevisionChanges
2018-08-1001-REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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  • corrected Bank Voltages for Bank 2J (VCCIO2J) and Bank 2K (VCCIO2K)
2022-03-18v.85Vitali Tsiukala
  • Added Info about Gigabit Transceivers
2021-06-07

v.84

Martin Rohrmüller
  • corrected Physical Dimension figure
  • updated to REV03

2020-01-17

v.82Martin Rohrmüller
  • updated to REV02

2019-06-14

v.80Pedram Babakhani

  • Figures updated

  • Technical specifications updated

2019-05-29

v.69Pedram Babakhani
  • initial release

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