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Intel® Cyclone 10 GX Industrial [10CX220YF780I5G]
- Package: FBGA-780
- Speed Grade: 5 (Fastest)
- Temperature: -40°C to 100°C
- Package compatible device 10CX150 and 10CX105 as assembly variant on request possible
2x SDRAM DDR3L Memory IC 8 Gbit (1 GByte), Half rate: 533 MHz; Quarter rate: max. 800 MHz
2x SPI Flash, 1 Gbit (128 MByte)
1x Gigabit Ethernet Programmable Oscillator
10-Channel, Any-Frequency, Any-Output Jitter Attenuator/Clock Multiplier
Intel® MAX 10 as System Controller (CPLD)
2 Kbit EEPROM Memory
4x User LED
I/O interfaces: 226/94/46 (IOs/DIFF. Pairs/LVDS Pairs)
12 x 12.5Gbps Transceiver
Board to Board (B2B) Connection: Plug-on module with 3 x 160-pin Samtec Razor Beam (ST5) connectors
5 V Power Supply
Dimension: 80m x 60m

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anchor	Figure_OV_BD
title	TEI0006 block diagram

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Main Components

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title	TEI0006 main components

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Intel® MAX 10, U18
DC/DC convertor, U4...11
SDRAM DDR3 Memory, U12 - U13
User LEDs, D1...4
Ethernet Transceiver, U2
SPI Flash Memory, U1 - U3
Intel® Cyclone 10 GX, U23
EEPROM, U64
Buffer, U16
10-Channel Clock Multiplier, U14
CryptoAuthentication Device (optional), U19

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module

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Storage device name	Content	Notes
Intel® MAX 10	Programmed	See CPLD Firmware
Quad SPI Flash	Not Programmed
EEPROM	Quad SPI Flash	Not Programmed	EEPROM	Programmed	Ethernet MAC
DDR3 SDRAM	Not Programmed

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anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

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FPGA	FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
Intel Cyclone 10 GX	Bank 1C	J3	24 Single ended (12 Diff pair)	0.95V	GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P
	Bank 1D	J3	24 Single ended (12 Diff pair)	0.95V	GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P
	Bank 2A	J2	2 Single ended	1.8V	PERST, CLKUSR
	Bank 2J	J2	46 Single ended (23 Diff pair)	VCCIO2J
	Bank 2K	J1	46 Single ended (23 Diff pair)	VCCIO2K
	Bank 2L	J1	48 Single ended (24 Diff pair)	VADJ up to 3 V
	Bank 3A	-	-	1.35V	VDD_DDR
	Bank 3B	-	-	1.35V	VDD_DDR
Intel Max 10	Bank 1A	J2	8 Single ended	3.3V
	Bank 1B	J2	5 Single ended	3.3V
	Bank 2	J3	2 1 Single ended	1.8VIO
	Bank 3	-	-	1.8VIO
	Bank 5	J2	4 3 Single ended	3.3V
	Bank 6	J2	2 Single ended	3.3V
	Bank 8	J2	24 23 Single ended	3.3V

JTAG Interface

JTAG access to the TEI0006 SoM is through B2B connector J2. JTAGEN is pulled up to 3.3V and after power on, JTAG will be enabledfor MAX 10 CPLD is enabled. JTAG port of Cyclon 10 GX device is routed to MAX10 CPLD IOs. The default Firmware connects the JTAG port of the Cyclon 10 GX to the IO pins of the JTAG port in user IO mode. Setting JTAGEN to GND enables JTAG for the Cyclon 10 GX device.

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title	JTAG pins connection

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JTAG Signal	B2B Connector	Note
TMS	J2-160
TDI	J2-159
TDO	J2-158
TCK	J2-157
JTAGEN	J2-105	Pulled up to 3.3V.

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO Pin

Connected to

B2B

Notes

MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2

QSPI

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MIO Pin	Connected to	B2B	Notes
MAX_IO1...20, 22	U18 (Intel MAX 10) - Bank 8	J2
MAX_IO23..., 25, 26	U18 (Intel MAX 10) - Bank 5	J2

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title	On board peripherals

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Chip/Interface	Designator	Notes
QSPI Flash Memory	U1 - U3	U1- AS configuration
EEPROM	U64
DDR3 SDRAM Memory	U12 - U13
Ethernet PHY	U2
Intel Max 10	U18	System controller
User LEDs	D1...4	D1 (Red), D2...4 (Green)
Oscillators	U14, U15, U17, U21, Y1
CryptoAuthentication Device	U19	optional

QSPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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Clock Sources

The TEI0006 has three crystal oscillator one crystal, three MEMS oscillators and a programmable clock generator.

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title	Osillators

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Designator	Description	Frequency

Note

Connected to
U21

Crystal

MEMS Oscillator	25MHz	U2 Ethernet
U15

Crystal

MEMS Oscillator	25MHz	IN0 of U14
U17	MEMS Oscillator	100 MHz	U23, BANK2A USRCLK
Y1	Crystal Oscillator

48MHz

50MHz	crystal input of U14
U14	Programmable Oscillator	Variable	-

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title	Programmable Oscillator connections

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Signals	Clock Type	In/ Out	Connected to	Frequency	Note
IN0_P IN0_N	Differential	In In	Oscillator, U15 GND	25 MHz
IN1..3 IN3	Differential	In	B2B, J3	Variable
XA, XB	Differential		Oscillator, U17Y1 GND	48 50 MHz
CLK0	Differential	Out	Intel Cyclon Cyclone 10 GX (U23)- Bank 2A	User	Default off
CLK1...4	Differential	Out	B2B, J3	User	Default off
REFCLK_EMIFP	Differential	Out	Intel Cyclon 10 GX (U23)- Bank 3B	User	Default off
CLK6...7	Differential	Out	Intel Cyclon 10 GX (U23)- Bank 1D	User	Default off
CLK8...9	Differential	Out	Intel Cyclon 10 GX (U23)- Bank 1C	User	Default off

Power and Power-On Sequence

CryptoAuthentication

ATECC608A (U19) is a CryptoAuthentication device connected to the I²C bus. This chip is optional, for further description see datasheet of manufacturer.

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title	I2C Interface of CryptoAuthentication

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Schematic	U19 Pin	B2B	U18 Intel Max 10 Pin	Notes
I2C_SCL	SCL	J3-135	Bank 2 - K2	-
I2C_SDA	SDA	J3-137	Bank 2 - L2	-

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

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anchor	Figure_PWR_PD
title	Power Distribution

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Power-On Sequence

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title	Power Sequence

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Power Rails

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title	Module power rails.

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Power Rail Name

B2B Connector

J1 Pin

B2B Connector

J2 Pin

B2B Connector

J3 Pin

Voltage Level

Direction

Notes

VIN

145, 147,149, 151, 153, 155, 157, 159

-

5 V

Input

VCCIO2K

53, 54

-

1.2 V, 1.25 V, 1.35

V, 1.5 V, 1.8

V,

2

1.5 V or

3

1.

0

8 V	Input
VADJ	140,142	-	-	adjustable between 1.8 V - 3.0 V	Output	Voltages according to EP53A8HQI datasheet but restricted to allowed bank voltage
VCCIO2J	-	29,30	-	1.2 V, 1.25 V, 1.35 V, 1.5 V

,

or 1.8

V, 2.5

V

or 3.0 V

	Input
3.3V	-	149,150	-	3.3 V	Output
1.8_VIO	-	-	139	1.8 V	Output

Bank Voltages

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anchor	Table_PWR_BV
title	SoC bank voltages.

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FPGA	FPGA Bank	Voltage Level	Notes
Intel Cyclone 10 GX	Bank 1C	0.95 V
	Bank 1D	0.95 V
	Bank 2A	1.8 V	1.8VIO
	Bank 2J	1.2 V, 1.25 V, 1.35 V, 1.5 V , or 1.8 V, 2.5 V or 3.0 V	VCCIO2J
	Bank 2K	1.2 V, 1.25 V, 1.35 V, 1.5 V , or 1.8 V, 2.5 V or 3.0 V	VCCIO2K
	Bank 2L	adjustable between 1.8 V - 3.0 V	Voltages according to EP53A8HQI datasheet
	Bank 3A	1.35 V	VDD_DDR
	Bank 3B	1.35 V	VDD_DDR
Intel Max 10	Bank 1A	3.3 V
	Bank 1B	3.3 V
	Bank 2	1.8 V	1.8VIO
	Bank 3	1.8 V	1.8VIO
	Bank 5	3.3V
	Bank 6	3.3V
	Bank 8	3.3V

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anchor	Figure_TS_PD
title	Physical Dimension

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Date	Revision	Changes	Documentation Link
202-12-23	03	two input cloock signals on B2B connected directly to GXBL1C bank	REV03
2019-09-11	02	added 100MHz MEMS oscillator, remove CLKUSR signal from J2 replaced U21/U15 by SiT8008 added pull-up to M10_NSTATUS signal added pull-up to M10_DEVCLRN, removed signal from J2 added optional CryptoAuthentication chip U19	REV02
Date	Revision	Changes	Documentation Link
2018-08-10	01	-	REV01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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anchor	Figure_RV_HRN
title	Board hardware revision number.

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Date

Revision

Contributor

Description

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infoType	Modified by
type	Flat
showVersions	false

corrected Bank Voltages for Bank 2J (VCCIO2J) and Bank 2K (VCCIO2K)

2022-03-18

v.85

Vitali Tsiukala

Added Info about Gigabit Transceivers

2021-06-07

v.84

Martin Rohrmüller

corrected Physical Dimension figure
updated to REV03

2020-01-17

v.82

Martin Rohrmüller

updated to REV02

2019-06-14

v.80

Pedram Babakhani

Figures updated
Technical specifications updated

2019-05-29

v.69

Pedram Babakhani

initial release

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Trenz Electronic Documentation

Versions Compared

Old Version 79

New Version Current

Key

Main Components

Initial Delivery State

JTAG Interface

QSPI Flash Memory

Clock Sources

Power and Power-On Sequence

CryptoAuthentication

Power and Power-On Sequence

Power-On Sequence

Power Rails

Bank Voltages