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changes.mady.by.user Martin Rohrmüller

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  • Intel® Cyclone 10 GX Industrial [10CX220YF780I5G]
    • Package: FBGA-780
    • Speed Grade: 5 (Fastest)
    • Temperature: -40°C to 100°C
    • Package compatible device 10CX150 and 10CX105 as assembly variant on request possible
  • 2x SDRAM DDR3L Memory IC 8 Gbit (1 GByte), Half rate: 533 MHz; Quarter rate: max. 800 MHz
  • 2x SPI Flash, 1 Gbit (128 MByte)
  • 1x Gigabit Ethernet Programmable Oscillator
  • 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/Clock Multiplier
  • Intel® MAX 10 as System Controller (CPLD)
  • 2 Kbit EEPROM Memory

  • 4x User LED 

  • I/O interfaces: 226/94/46 (IOs/DIFF. Pairs/LVDS Pairs)
  • 12 x 12.5Gbps Transceiver

  • Board to Board (B2B) Connection: Plug-on module with 3 x 160-pin Samtec Razor Beam (ST5) connectors

  • 5 V Power Supply

  • Dimension: 80m x 60m

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Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

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FPGAFPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes

Intel Cyclone 10 GX

Bank 1C

J3

24 Single ended (12 Diff pair)

0.95V

GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P

Bank 1D

J3

24 Single ended (12 Diff pair)

0.95V

GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P

Bank 2A

J2

2 Single ended

1.8V

PERST, CLKUSR

Bank 2J

J2

46 Single ended (23 Diff pair)

VCCIO2J


Bank 2K

J1

46 Single ended (23 Diff pair)

VCCIO2K


Bank 2L

J1

48 Single ended (24 Diff pair)

VADJ up to 3 V


Bank 3A

-

-

1.35V

VDD_DDR

Bank 3B

-

-

1.35V

VDD_DDR

Intel Max 10

Bank 1A

J2

8 Single ended

3.3V


Bank 1B

J2

5 Single ended

3.3V


Bank 2

J3

1 Single ended

1.8VIO


Bank 3

-

-

1.8VIO


Bank 5

J2

3 Single ended

3.3V


Bank 6

J2

2 Single ended

3.3V


Bank 8

J2

23 Single ended

3.3V



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Page properties
hiddentrue
idComments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



Scroll Title
anchorTable_OBP_MIOs
titleMIOs pins

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MIO PinConnected toB2BNotes
MAX_IO1...20, 22U18 (Intel MAX 10) - Bank 8J2
MAX_IO23, 25, 26U18 (Intel MAX 10) - Bank 5
J2


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Scroll Title
anchorTable_OBP_CLK_PO
titleProgrammable Oscillator connections

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SignalsClock TypeIn/ OutConnected toFrequencyNote

IN0_P

IN0_N

Differential

In

In

Oscillator, U15

GND

25 MHz
IN3 DifferentialInB2B, J3Variable

XA, XB

Differential

Oscillator, Y1

50 MHz

CLK0

DifferentialOutIntel Cyclon Cyclone 10 GX (U23)- Bank 2AUserDefault off

CLK1...4

DifferentialOutB2B, J3UserDefault off
REFCLK_EMIFPDifferentialOutIntel Cyclon 10 GX (U23)- Bank 3BUserDefault off
CLK6...7DifferentialOutIntel Cyclon 10 GX (U23)- Bank 1DUserDefault off
CLK8...9DifferentialOutIntel Cyclon 10 GX (U23)- Bank 1CUserDefault off


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Scroll Title
anchorTable_PWR_PR
titleModule power rails.

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Power Rail Name

B2B Connector

J1 Pin

B2B Connector

J2 Pin

B2B Connector

J3 Pin

Voltage LevelDirectionNotes
VIN145, 147,149, 151, 153, 155, 157, 159--5 VInput
VCCIO2K53, 54--1.2 V, 1.25 V, 1.35 V, 1.5 V
,
or 1.8 V
, 2.5 V or 3.0 V
Input
VADJ140,142--adjustable between 1.8 V - 3.0 VOutputVoltages according to EP53A8HQI datasheet but restricted to allowed bank voltage
VCCIO2J-29,30-1.2 V, 1.25 V, 1.35 V, 1.5 V
,
or 1.8 V
, 2.5 V or 3.0 V
Input

3.3V

-149,150-3.3 VOutput
1.8_VIO--1391.8 VOutput


Bank Voltages

Scroll Title
anchorTable_PWR_BV
titleSoC bank voltages.

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FPGAFPGA BankVoltage LevelNotes
Intel Cyclone 10 GXBank 1C0.95 V

Bank 1D

0.95 V
Bank 2A1.8 V1.8VIO
Bank 2J1.2 V, 1.25 V, 1.35 V, 1.5 V , or 1.8 V, 2.5 V or 3.0 VVCCIO2J
Bank 2K1.2 V, 1.25 V, 1.35 V, 1.5 V , or 1.8 V, 2.5 V or 3.0 VVCCIO2K
Bank 2Ladjustable between 1.8 V - 3.0 VVoltages according to EP53A8HQI datasheet
Bank 3A1.35 VVDD_DDR
Bank 3B1.35 VVDD_DDR
Intel Max 10Bank 1A3.3 V
Bank 1B3.3 V
Bank 21.8 V1.8VIO
Bank 31.8 V1.8VIO
Bank 53.3V
Bank 63.3V
Bank 83.3V


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Scroll Title
anchorTable_RH_DCH
titleDocument change history.

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DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

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infoTypeModified by
typeFlat
showVersionsfalse

  • corrected Physical Dimensio Bank Voltages for Bank 2J (VCCIO2J) and Bank 2K (VCCIO2K)
2022-03-18v.85Vitali Tsiukala
  • Added Info about Gigabit Transceivers
2021-06-07

v.84

Martin Rohrmüller
  • corrected Physical Dimension figure
  • updated to REV03

2020-01-17

v.82Martin Rohrmüller
  • updated to REV02

2019-06-14

v.80Pedram Babakhani

  • Figures updated

  • Technical specifications updated

2019-05-29

v.69Pedram Babakhani
  • initial release

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infoTypeModified users
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