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DateVivadoProject BuiltAuthorsDescription
2018-10-312018.2

TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip

TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip

John Hartfiel
  • new assembly variants
  • update optional petalinux startup init script
2018-09-122018.2TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip
TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip
John Hartfiel
  • correction:
    • TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
    • small changes on DDR setup of TE0820-02-2EG-1EE
2018-08-152018.2TE0820-test_board-vivado_2018.2-build_01_20180706212937.zip
TE0820-test_board_noprebuilt-vivado_2018.2-build_01_20180706212952.zip
John Hartfiel
  • different design for REV03
  • small petalinux changes
  • IO renaming
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-06-192017.4TE0820-test_board-vivado_2017.4-build_10_20180619160713.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180619160728.zip
John Hartfiel
  • bugfix board part files BANK1 MIO voltages
  • Add "dummy" PS USB3 parameter so solve problems with some USB2 devices
2018-05-242017.4

TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip

John Hartfiel
  • solved Linux Flash issue
  • new assembly variant
2018-04-252017.4TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip
John Hartfiel
  • new assembly variants
2018-02-062017.4TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip
John Hartfiel
  • solved JTAG/Linux issue
2018-02-012017.4TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip
John Hartfiel
  • board part csv update
2018-01-242017.4TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip
John Hartfiel
  • rework board part files
  • solved  USB, QSPI and PHy issue
2017-11-212017.2TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip
John Hartfiel
  • solved SD SDX Cards Problem
  • Separate csv name for all assembly variants
2017-11-202017.2TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip
John Hartfiel
  • solved SD WP Problem
2017-10-192017.2TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip
John Hartfiel
  • initial release

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0820-ES1 es1REV011GB64
  •  use slower DDR speed
  • Xilinx has stopped ES1 support with 2018.2, please use 2017.4 reference design for ES1
TE0820-02-2EG-1E2eg_1eREV021GB64

TE0820-02-2EG-1E32eg_1eREV021GB642.5 mm Samtec connectors
TE0820-02-2EG-1EA2eg_1eREV021GB128TE0820-02-2EG-1EE2eg_1eeREV022GB128

TE0820-02-2EG-1EL2eg_1eREV021GB1282.5 mm Samtec connectors

TE0820-02-2CG-1E

2cg_1eREV021GB64

TE0820-02-2CG-1EA2cg_1eREV021GB128

TE0820-02-3EG-1E3eg_1eREV021GB64

TE0820-02-3EG-1E33eg_1eREV021GB642.5 mm Samtec connectors
TE0820-02-3EG-1EA3eg_1eREV021GB128

TE0820-02-3EG-1EL3eg_1eREV021GB1282.5 mm Samtec connectors
TE0820-02-3CG-1E3cg_1eREV021GB64

TE0820-02-3CG-1EA3cg_1eREV021GB128

TE0820-02-4CG-1EA4cg_1eREV021GB128

TE0820-03-4EV-1EA4ev_1e_2gbREV032GB12864

TE0820-0203-3CG2CG-1EA3cg2cg_1e_2gbREV02REV031GB2GB128

TE0820-0203-4CG2EG-1EA4cg2eg_1e_2gbREV02REV031GB2GB128

TE0820-03-4EV2EG-1EA1EL4ev2eg_1e_2gbREV032GB1282.5 mm Samtec connectors

Design supports following carriers:

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TypeLocationNotes
SI5338<design name>/misc/Si5338SI5338 Project with current PLL Configuration
init_script<design name>/misc/init_scriptoptional init script for SD card

Prebuilt

HTML
<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

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DateDocument RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.



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modified-user
modified-user

  • Update Design files for 2GB variants
  • rebuilt petalinux for optional init script

v.41John Hartfiel
  • Update Design files for 2GB variants

v.4140John Hartfiel
  • add notes to ES1

v.38John Hartfiel
  • 2018.2 release finished

v.34John Hartfiel
  • Design Files Update

v.29John Hartfiel
  • Design Files Update
2018-02-06v.27John Hartfiel
  • Design Files Update
2018-01-29v.26John Hartfiel
  • Update Known Issues
2018-01-24v.25John Hartfiel
  • Release 2017.4
2018-01-10v.24John Hartfiel
  • Update Known Issues
2017-12-20v.23John Hartfiel
  • Typo correction
  • Update HW Module Table Description
2017-11-21

v.19

John Hartfiel
  • Design Update
2017-11-20v.18John Hartfiel
  • Design Update
  • Add Variants with 128MB Flash
2017-11-13v.16John Hartfiel
  • Update Carrier sections
2017-11-06v.15John Hartfiel
  • Typo corrected
2017-10-23v.13John Hartfiel
  • Update Key Features section
  • Style Update Additional Software section
2017-10-19
v.9
John Hartfiel
  • Release 2017.2
2017-09-11v.1

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created-user

Initial release

All

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