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The Trenz Electronic TEF1002-02 ... is an industrial-grade ... module ... based on Xilinx ...carrier is a baseboard for Trenz Electronic 4 x 5 SoMs.  It is a PCIe x1 card and also hosts and LPC FMC connector.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEF1002 carrier board.

Refer to trenz.org/tef1002-info for Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.

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  1. ANSI/VITA 57.1 compliant FMC LPC connector, J1
  2. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
  3. SFP+ connector, J12
  4. PCIe x1 connector, J3
  5. SATA connector with pin 7 power configuration, J31
  6. Trenz Electronic 4 x 5 modules B2B connectors, JB1 ... JB3
  7. RJ45 Gigabit Ethernet connector, J9
  8. 2x high speed LVDS arrangement of connectors J11, J13, J14, J18
  9. Micro-USB2 connector, J10
  10. FTDI FT2232H USB2 to JTAG,UART/FIFO Bridge, U4
  11. Micro-USB2 connector, J16
  12. MAX10 10M08SAU169C8G CPLD, U11
  13. 6-pin 12V power connector, J15
  14. 5x2 CPLD JTAG pin header for TEI0004, J5
  15. 3x1 jumper pin header (select VCCIOA), J4
  16. 3x1 jumper pin header (select VCCA_SD), J7
  17. 3x1 pin header (VBAT), J6
  18. 2x3 pin header (MIO/PJTAG), J19
  19. Push button, S1
  20. 10x dip switch, S2, S3
  21. DCDC LTM4638 @5.0V, U9
  22. DCDC EN6338QI @3.3V, U10
  23. 2x green LED (user), D1, D2
  24. green LED (Power), D3
  25. green LED (Status), D4
  26. SD-Card connector (top loader),
  27. DCDC EN5335QI (FMC_VADJ), U1
  28. DCDC EN6338QI @3.3V (3V3FMC), U14
  29. SDIO Level shifter TXS02612, U3

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Scroll Title
anchorTable_SIP_PCIe
titlePCIe x1 card edge connector

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Connector J3 Pins and InterfacesI/O Signal Countdiff.-pairs countConnected toVCCIO voltageNotes
Multi Gigabit Transceiver-2B2B JB3 connector, pin 25, 27 and 26, 28-RX, TX
Clock-1B2B JB3 connector, pin 32, 34-
JTAG5-SC CPLD U11, M12, M13, L11, N12, G103V3INTDO, TMS, TCK, TDI, TRST


SATA connector

The SATA connector includes the pin 7 power configuration. This means that pin 7 (usually GND) is connected to a power switch U15, applying 5V to this pin. This gives the possibility to use SATADoMs with pin 7 power configuration. If a standard SATA device is connected the short (Current >0.5A) of Pin7 to GND is detected by the powerswitch and the powerswitch is switched OFF by the CPLD until a powercycle of TEF1002. There is also the possibility to remove the pin 7 power configuration by removing R82 and assembling R83 (0 Ohm, 2012 (0805)).

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titleSATA connector

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titleSATA connector

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RX, TX
Connector J31 Pins and InterfacesI/O Signal Countdiff.-pairs countConnected toVCCIO voltageNotes
Multi Gigabit Transceiver, pin 5,6 and 2,3-2B2B JB3 connector, pin 7, 9 and 8, 10--RX, TX
Pin 1,4--GNDGND-
Pin 7--U15, pin 6,85V0_SATAConnetion is via R82 0 Ohm resistor.


High speed connectors FFA and FFB

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Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing . Doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

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anchorTable_OBP_FTDI
titleFT2232H interface connections

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FTDI U4 pinSignal Schematic NameConnected to,  PinFunctionNotes
Pin 22ACBUS0SC CPLD U4, A4GPIO's available to user











(FIFO or other FTDI functions when FTDI reprogrammed)











Pin 23ACBUS1SC CPLD U4, B4
Pin 24ACBUS2SC CPLD U4, A5
Pin 25ACBUS3SC CPLD U4, B5
Pin 26ACBUS4SC CPLD U4, A6
Pin 27ACBUS5SC CPLD U4, B6
Pin 28ACBUS6SC CPLD U4, A7
Pin 29ACBUS7SC CPLD U4, A8
Pin 17ADBUS4SC CPLD U4, A2
Pin 18ADBUS5SC CPLD U4, B2
Pin 19ADBUS6SC CPLD U4, A3
Pin 20ADBUS7SC CPLD U4, B3
Pin 12F_TCKSC CPLD U4, G2H3JTAG signals forward to SC CPLD U4

(FIFO or other FTDI functions when FTDI reprogrammed)

Pin 13F_TDISC CPLD U4, F5H2
Pin 14F_TDOSC CPLD U4, F6G4
Pin 15F_TMSSC CPLD U4, G1F4
Pin 32BDBUS0JB1, 91UART
Pin 33BDBUS1JB1, 86


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anchorTable_OBP_SDIO
titleSDIO Port Expander connections

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Port Expander U3 pinSignal Schematic NameConnected to B2B  PinNotes
Pin 6SD-D0JB1, Pin 24Signals levelshiftet to 3.3V and connected to Card card holder (J8)
Pin 7SD-D1JB1, Pin 22
Pin 1SD-D2JB1, Pin 20
Pin 3SD-D3JB1, Pin 18
Pin 4SD-CMDJB1, Pin 26
Pin 9SD-CCLKJB1, Pin 28


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anchorTable_OBP_DIPs
titleDIP-switches

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SwitchSignal Schematic NameConnected to,  PinNotes
S2-1VID0SC CPLD U11, K6SC CPLD firmware dependent, used for FMC_VADJ, see table below. Select according to the IO capabilites of attached 4x5 SoM and FMC.
S2-2VID1SC CPLD U11, N5
S2-3VID2SC CPLD U11, N4
S2-4JTAGENSC CPLD U11, E5ON TEF1002 SC CPLD JTAG; OFF CPLD IOs, hard wired.
S2-5M_JTAGENJB1, Pin 90When S2-6 OFF: OFF 4x5 module  FPGA/SOC JTAG, ON 4x5 module CPLD JTAG, hard wired.
S2-6FMC_JTAGSC CPLD U11, L3SC CPLD firmware dependent. ON: FMC JTAG; OFF 4x5 module JTAG, see S2-5.
S2-7

CM0

SC CPLD U11, M3SC CPLD firmware dependent, EN1
S2-8CM1SC CPLD U11, L2SC CPLD firmware dependent, NOSEQ
S3-1CM2SC CPLD U11, K2SC CPLD firmware dependent, BOOT MODE
S3-2USR0SC CPLD U11, K1SC CPLD firmware dependent, Override FMC_EN_VADJ


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anchorTable_OBP_Jumper
titleJumper positions

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JumperPower rail3.3V1.8VRemark
J4VCCIOA1-22-3Powers 4x5 bank, where FFA and FFB high speed signals are connected.
J7VCCA_SD1-22-3Powers SDIO Levelshifter on 4x5 module side.


Push Button

There is on push button (S1) on the TEF1002. It is connected to the SC CPLD (U11 Pin N6). The function is firmware dependet. In the actual delivery firmware it is used as module reset connected to B2B JB2 Pin 17 (RESIN). For further descriptions see firmware description.

Pin Header

Pin header J5 (can be used with TEI0004 programming module or any other Quartus compatible JTAG programmer) for MAX10 CPLD Firmware programming. If dip switch S2-4 is set to OFF, JTAG pins can also be used as CPLD IOs, e.g. routed to FMC JTAG or as IO extension (not implemented in standard firmware).

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Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


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Power-On Sequence

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anchorFigure_PWR_PS
titlePower Sequency


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Power Rails


In the following table power rails acceccible for in or output on any connectors are summarized.

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titlePower Rails

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Connector, PinsVoltageDirectionNotes
J15, 1,2,312VINTEF1002 supply voltage
J16, 15VOUTUSB-VBUS_R
J6, 1Depends on 4x5 ModuleINDirectly connected to B2B PSBATT pin
J2, 25VOUTFMC Fan Connector
JB1, 10,121,8V/3.3VOUTVCCIOA, selected by J4
JB1, 14,163.3VOUTModule supply voltage
JB1, 401.8VINModule 1.8V output
JB1, 80Depends on 4x5 ModuleOUTDirectly connected to pinheader J6 PSBATT
JB1, 2,4,65VOUTModule power input
JB2, 1,3,5,75VOUTModule power input
JB2, 9,113.3VINModule 3.3V output
JB2, 2,4,6,8,100,8V ... 3.3VOUTModule VCCIOB, VCCIOC, VCCIOD connected to FMC VADJ
JB2, 20Depends on 4x5 ModuleINModule DDR power output
JB2, 92Depends on 4x5 ModuleINVREF_JTAG
J13, 1,103.3VOUTFFA supply voltages
J18, 1,103.3VOUTFFB supply voltages



Page properties
hiddentrue
idComments
  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
    Include Page
    PD:4 x 5 SoM LSHM B2B ConnectorsPD:
    4 x 5 SoM LSHM B2B Connectors

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Scroll Title
anchorFigure_RH_HRN
titleHardware Revision Number
draw.io Diagram
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diagramWidth406360
revision12

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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anchorTable_RH_DCH
titleDocument change history.

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DateRevisionContributorDescription

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infoTypeModified date
dateFormatyyyy-MM-dd
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infoTypeModified by
typeFlat
showVersionsfalse

  • typo correction

2020-01-29v.28Martin Rohrmüller
  • updated to REV02
2019-09-06v.25Martin Rohrmüller
  • initial version

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infoTypeModified users
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