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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

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          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
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Notes :

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...TEF1002-02 carrier is a baseboard for Trenz Electronic 4 x 5 SoMs.  It is a PCIe x1 card and also hosts and LPC FMC connector.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEF1002 carrier board.

Refer to trenz.org/tef1002-info for Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.

...

  • Carrier for 4x5 modules

  • LPC FMC

  • SFP+ connector
  • PCIe x1
  • SATA connector with pin 7 power configuration for SATADoM
  • RJ45 Gigabit Ethernet connector
  • micro-usb to JTAG/UART bridge
  • 2x 8 lane high speed LVDS connectors (firefly)
  • micro usb connector
  • micro SD card connector
  • 4x LED (2User, Power and Status)
  • Module reset button
  • 10x configuration/user dip switch

  • MAX10 CPLD

Block Diagram

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titleTE... TEF1002 block diagram


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Main Components

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titleTE... TEF1002 main components


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  1. ANSI/VITA 57.1 compliant FMC LPC connector, J1
  2. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
  3. SFP+ connector, J12
  4. PCIe x1 connector, J3
  5. SATA connector with pin 7 power configuration, J31
  6. Trenz Electronic 4 x 5 modules B2B connectors, JB1 ... JB3
  7. RJ45 Gigabit Ethernet connector, J9
  8. 2x high speed LVDS arrangement of connectors J11, J13, J14, J18
  9. Micro-USB2 connector, J10
  10. FTDI FT2232H USB2 to JTAG,UART/FIFO Bridge, U4
  11. Micro-USB2 connector, J16
  12. MAX10 10M08SAU169C8G CPLD, U11
  13. 6-pin 12V power connector, J15
  14. 6x1 5x2 CPLD JTAG pin header (not fitted)for TEI0004, J5
  15. 3x1 jumper pin header (select VCCIOA), J4
  16. 3x1 jumper pin header (select VCCA_SD), J7
  17. 2x1 3x1 pin header (VBAT), J6
  18. 2x5 1,27mm pitch 2x3 pin header (MIO/PJTAG), J19
  19. Push button, S1
  20. 10x dip switch, S2, S3
  21. DCDC LMZ23605TZ LTM4638 @5.0V (5V0PER), U15DCDC LMZ23605TZ @5.0V (5V0), U9
  22. DCDC LMZ23605TZ EN6338QI @3.3V(3V3IN), U10
  23. 2x green LED (user), D1, D2
  24. green LED (Power), D3
  25. green LED (Status), D4
  26. SD-Card connector (top loader),
  27. DCDC EN5335QI (FMC_VADJ), U1
  28. DCDC EN6338QI @3.3V (3V3FMC), U14
  29. SDIO Level shifter TXS02612, U3

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titleInitial delivery state of programmable devices on the module.

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Storage device name

Content

Notes

FTDI chip configuration EEPROM (93AA56B), U6

Xilinx License

Do not overwrite, see warning in related section
MAX10 System Controller CPLD (10M08SAU169C8G), U14SC CPLD Firmware


...

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titleTEF1002 Control Signals

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Control signal

Switch / Button / LED / PinSignal Schematic Names

Connected to

Functionality

Notes
FMC_VADJ voltage selectionDIP switches S2-1, S2-2, S2-3VID0 ... VID2SC CPLD U11, pins K6, J5, K5sets adjustable voltage for FMC connectordependens on SC CPLD configuration
JTAG enableDIP switch S2-4JTAGENSC CPLD U11, pin E5

OFF:  CPLD IOs
ON: TEF1002 SC CPLD JTAG enabled,ON: Module/FMC JTAG enabled

-

function in OFF position  depends on SC CPLD configuration (JTAG on pin header J5 (for TEI0004)

Module JTAG selectDIP switch S2-5

M_JTAGEN

B2B JB1, pin 90

When S2-4 ON and S2-6 OFF:

OFF: Module SC CPLD SOC JTAG enabled,

ON: Module SOC SC CPLD JTAG enabled

-		(JTAG via micro USB J10)
FMC JTAG selectDIP switch S2-6FMC_JTAGSC CPLD U11,L3

When S2-4 ON:

OFF: TEF1002 SC CPLD Module JTAG enabled ,(see S2-5)

ON: FMC JTAG enabled

depends on SC CPLD configuration,

only avialiable when 4x5 module installed

(JTAG via micro USB J10)

Enable module powerDIP switch S2-7CM0SC CPLD U11, M3Module power. Set ON to enable module power. (Power management depends on module. )depends on SC CPLD configuration, only avialiable when 4x5 module installed
No sequenzingDIP switch S2-8CM1SC CPLD U11, L2Module Power management. Set ON to disable module CPLD power management. Power management depends on module and not all modules support extended power management with CPLD.depends on SC CPLD configuration, only avialiable when 4x5 module installed
Boot ModeDIP switch S3-1CM2SC CPLD U11, K2

Boot Mode for attached module (Default: OFF for primary SD boot and ON for primary QSPI boot. Depends also on module CPLD firmware).

depends on SC CPLD configuration, only avialiable when 4x5 module installed
FMC VADJ enableDIP switch S3-2USR0SC CPLD U11, K1

ON: FMC VADJ enable also without installed FMC Card

OFF: FMC_FADJ only enabled when FMC installed.

dependens on SC CPLD configuration, only avialiable when 4x5 module installed
ResetPush button S1BUTTONSC CPLD U11, N6Module Reset, Low active module reset. Pin force Power one reset on FPGA/SoC.depends on SC CPLD configuration
2x User LEDGreen LEDs D1, D2LED1, LED2SC CPLD U11, J5, K5Depends on User configuration, curenntly both off, if not otherwise programmed.depends on SC CPLD configuration
Board power indicatorGreen LED D33V3INB2B JB1, pin 14, 16

ON: 3.3V on-board voltage available

-
Board status indicatorsGreen LED D4-SC CPLD U11, pin C2

ON: No failure. For other blinking status of this LED please refer to SC Firmware description.

dependens on SC CPLD configuration
Enable module powerSC CPLD U11, D11EN1B2B JB1, pin 27Module power.  (Power management depends on module. )-In standard Firmware  connected to CM0 (see above)
No sequenzingNo sequenzingSC CPLD U11, E13NOSEQB2B JB1, pin 8Power management depends on module and not all modules support extended power management with CPLD.-In standard Firmware  connected to CM1 (see above)
Boot ModeSC CPLD U11, B11MODEB2B JB1, pin 31Boot Mode for attached module. LOW for primary SD boot and HIGH for primary QSPI boot. (Depends also on module CPLD firmware).-In standard Firmware  connected to CM2 (see above)
Module ResetSC CPLD U11, E12RESINB2B JB2, pin 17Module Reset-In standard Firmware  connected to BUTTON S1  (see above)


Signals, Interfaces and Pins

...

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titleGeneral overview of B2B connectors

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B2B ConnectorInterfacesI/O Signal CountNotes
JB1User IO15 single ended or 7 differentialTEF1002 CPLD


16 single ended or 8 differentialFFA


16 single ended or 8 differentialFFB

MIO/PJTAG/User IO4Pinheader J19

CPLD IO2Module CPLD IO to Carrier CPLD

SD IO6-

UART2-

GbE PHY_MDIO + PHY_COM8 +1-

Module Control5NOSEQ,, EN1, PGOOD, MODE, M_JTAGEN

JB2JB3

User IO12 single ended or 6 differentialLPC FMC

MGTs (RX+TX)4PCIe x1, SFP+, LPC FMC, SATA

MGTCLK

1 differential-

CLK1 differential-

USB21 differnetialOTG-D_P, OTG-D_N

USB Control3OTG-ID
JB3JB2User IO56 single ended or 28 differential

LPC FMC


CLK2 differentialM2C

JTAG4-


...

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titleFMC connector interface

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FMC Connector J2 Pins and InterfacesI/O Signal CountLVDSdiff.-pairs countConnected toVCCIO voltageNotes
I/O5628B2B JB2 connectorFMC_VADJpins usable as single ended I/O's or LVDS differential pairs
126B2B JB3 connectorFMC_VADJ
Multi Gigabit Transceiver-2B2B JB3 connector,  pin 19, 21 and 20, 22-RX, TX
Gigabit Transceiver Clock-1B2B JB3 connector, pin 31, 33-
I²C (SDA, SCL)2-SC CPLD U11, pin F9, J83V3INFMC I²C Geographical Address pins GA0 and GA1 set to GND.
JTAG5-SC CPLD U11, pin N7, M8, F8, M7, N83V3INTDO, TMS, TCK, TDI, TRST
Clock Input-2B2B JB3 connectorFMC_VADJ2x reference clock inputs
Control Signals2-SC CPLD U11, pin M5, E93V3IN

'PG_C2M',  'FMC_PRSNT'

Reference voltage (FMC_VREF)----Not Connected.


...

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titleSFP+ interface

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Connector J12 Pins and InterfacesI/O Signal CountLVDSdiff.-pairs countConnected toVCCIO voltageNotes
Multi Gigabit Transceiver-2B2B JB3 connector, pin 13, 15 and 14, 16-RX, TX
Control6
SC CPLD U113V3INTX_FAULT, TX_DIS, M-DEF0, RS0, RS1, LOS
I²C (SDA, SCL)2-SC CPLD U11, pin F9, J83V3INMUX via CPLD


...

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titlePCIe x1 card edge connector

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Connector J3 Pins and InterfacesI/O Signal CountLVDSdiff.-pairs countConnected toVCCIO voltageNotes
Multi Gigabit Transceiver-2B2B JB3 connector, pin 725, 9 27 and 826, 1028-RX, TX
Clock-1B2B JB3 connector, pin 32, 34-
JTAG5-SC CPLD U11, M12, M13, L11, N12, G103V3INTDO, TMS, TCK, TDI, TRST


SATA connector

The SATA connector includes the pin 7 power configuration. This means that pin 7 (usually GND) is connected to a power switch U15, applying 5V to this pin. This gives the possibility to use SATADoMs with pin 7 power configuration. If a standard SATA device is connected the short (Current >0.5A) of Pin7 to GND is detected by the powerswitch and the powerswitch is switched OFF by the CPLD until a powercycle of TEF1002. There is also the possibility to remove the pin 7 power configuration by removing R82 and assembling R83 (0 Ohm, 2012 (0805)).

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titleSATA connector

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Connector J31 Pins and InterfacesI/O Signal Countdiff.-pairs countConnected toVCCIO voltageNotes
Multi Gigabit Transceiver, pin 5,6 and 2,3-2B2B JB3 connector, pin 7, 9 and 8, 10-RX, TX
Pin 1,4--GNDGND-
Pin 7--U15, pin 6,85V0_SATAConnetion is via R82 0 Ohm resistor.


High speed connectors FFA and FFB

There are two Firefly connector arrangements.

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Connector, Pins and InterfacesI/O Signal Countdiff.-pairs countConnected toVCCIO voltageNotes
FFA, J11-8B2B JB1 connector--
FFA Control, J144-SC CPLD U11, pin C10, C9, E8, B93V3INMPRS, MSEL, INTL, RSTL
FFA I2C, J142-SC CPLD U11, pin E6, D63V3IN
FFB, J11-8

B2B JB1 connector

--
FFB Control, J144-SC CPLD U11, pin A11, B10, A10, B93V3INMPRS, MSEL, INTL, RSTL
FFB I2C, J142-SC CPLD U11, pin A9, D83V3IN


The RSTL of both connectors are tied together.

microUSB JTAG/UART/FIFO Interface

The microUSB connector provides JTAG access to Module and FMC through the carriers USB to JTAG/UART/FIFO bridge. JTAG is routed for MUX to the CPLD. UART signals are connected to the module B2B connectors. For further description of the JTAG MUX see dip switches or SC CPLD Firmware.  For other non-standard functionalitiers compare on-board connection and datasheet of FTDI FT2232H.

(CPLD JTAG access is via 2x5 pin header J5. See pin header description)

microUSB

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titleMicroUSB J16

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Connector J16, Pins and InterfacesI/O Signal CountLVDS-pairs countConnected toVCCIO voltageNotes
DATA-1B2B JB3 connector, pin 48, 50--
Power, Control3-B2B JB3 pin 52, 54, 56-OTG-ID, VBUS_V_EN, USB-VBUS


RJ45 - Ethernet MagJack

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titleGigabit Ethernet Connector

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Scroll Title
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titleSATA connector

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Connector J31 J9, Pins and InterfacesI/O Signal CountLVDS-pairs countConnected toVCCIO voltageNotes
Multi Gigabit Transceiver-2B2B JB3 connector, pin 7, 9 and 8, 10-RX, TX

LVDS high speed connectors FFA and FFB

toVCCIO voltageNotes
PHY_MDI-4B2B JB1 connector, pin 3, 5, 9, 11, 15, 17, 21, 23--
LED12-SC CPLD U11, pin B13, C123V3INgreen/yellow
LED22
SC CPLD U11, pin D12, C133V3INgreen/yellow


micro SD-Card connector

The micro SD-Card connector J8 is connected to a TXS02612 SDIO port expander, which is used as levelshifter. Depending on the modules IO Voltage of the IO Bank where the SD-Card is connected Jumper J7 has to be setThere are two connector arrangements mechanical compatible to Firefly connectors, but with high speed LVDS signals.

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titleFMC micro SD-Card connector interface

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Connector , Pins and InterfacesI/O Signal CountLVDS-pairs countConnected toVCCIO voltageNotes
FFA, J11-8B2B JB1 connector--
FFA Control, J144-SC CPLD U11, pin C10, C9, E8, B93V3INMPRS, MSEL, INTL, RSTL
FFA I2C, J142-SC CPLD U11, pin E6, D63V3IN
FFB, J11-8

B2B JB1 connector

--
FFB Control, J144-SC CPLD U11, pin A11, B10, A10, B93V3INMPRS, MSEL, INTL, RSTL
FFB I2C, J142-SC CPLD U11, pin A9, D83V3IN

The RSTL of both connectors are tied together.

microUSB JTAG/UART/FIFO Interface

The microUSB connector provides JTAG access through the carriers USB to JTAG/UART/FIFO bridge. JTAG is routed for MUX and CPLD JTAG access to the CPLD. UART signals are connected to the module B2B connectors. For further description of the JTAG MUX see Dip switches or SC CPLD Firmware.  For non-standard functionalitiers compare on-board Peripherals and datasheet of FTDI FT2232H.

microUSB

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anchorTable_SIP_USB
titleMicroUSB J16

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J8 pinSignal Schematic Name
Muxed to signal on Port ExpanderConnected toNotes
2, DAT3

SD-D3_LS

SD_D3B2B JB1, pin 18-

3, CMD

SD-CMD_LS

SD_CMD

B2B JB1, pin 26-

5, CLK

SD-CCLK_LS

SD_CCLK

B2B JB1, pin 28-

7, DAT0

SD-D0_LS

SD_D0

B2B JB1, pin 24-

8, DAT1

SD-D1_LS

SD_D1

B2B JB1, pin 22-

1, DAT2

SD-D2_LS

SD_D2

B2B JB1, pin 20-
9, CARD detectSD-CD-U11, pin M1CPLD Firmware dependent, in default firmware not used


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

System Controller CPLD MAX10

The Intel/Altera MAX10 10M08SAU169C8G System Controller CPLD (U11) is the central system management unit where essential control signals are logically linked by the CPLD firmware. It generates output signals to control the system, the on-board peripherals and the interfaces. The JTAG and I2C between the on-board peripherals and the attached module are forwarded and controlled by the System Controller CPLD. A main tasks of the System Controller CPLD is the monitoring of the power-on sequence and configuring the state of the attached module. For detailed information, refer to the firmware documentation of the SC CPLD. Table below lists the SC CPLD I/O signals and pins:

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titleGigabit Ethernet ConnectorSC CPLD pin mapping

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Connector J9, Pins and InterfacesI/O Signal CountLVDS-pairs countConnected toVCCIO voltageNotes
PHY_MDI-4B2B JB1 connector, pin 3, 5, 9, 11, 15, 17, 21, 23--
LED12-SC CPLD U11, pin B13, C123V3INgreen/yellow
LED22SC CPLD U11, pin D12, C133V3INgreen/yellow

micro SD-Card connector

The micro SD-Card connector J8 is connected to a TXS02612 SDIO port expander, which is used as levelshifter. Depending on the modules IO Voltage of the IO Bank where the SD-Card is connected Jumper J7 has to be set.

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anchorTable_SIP_SDC
titlemicro SD-Card connector

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SD-D3_LS

...

3, CMD

...

SD-CMD_LS

...

SD_CMD

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5, CLK

...

SD_CCLK

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7, DAT0

...

SD-D0_LS

...

SD_D0

...

8, DAT1

...

SD_D1

...

1, DAT2

...

SD_D2

...

Signal nameSC CPLD PinConnected toFunctionNotes
ACBUS0A4FTDI U4, pin 22GPIO's available to user











(FIFO or other FTDI functions when FTDI reprogrammed)











ACBUS1B4FTDI U4, pin 23
ACBUS2A5FTDI U4, pin 24
ACBUS3B5FTDI U4, pin 25
ACBUS4A6FTDI U4, pin 26
ACBUS5B6FTDI U4, pin 27
ACBUS6A7FTDI U4, pin 28
ACBUS7A8FTDI U4, pin 29
ADBUS4A2FTDI U4, pin 17
ADBUS5B2FTDI U4, pin 18
ADBUS6A3FTDI U4, pin 19
ADBUS7B3FTDI U4, pin 20
TCKG2J5, 1CPLD JTAG signals from pin header



Other functions possible with non standard CPLD firmware.



TDIF5J5, 9
TDOF6J5, 3
TMSG1J5, 5
F_TCKH3FTDI U4, pin 12Forwarded JTAG signals from FTDI chip.(FIFO or other FTDI functions when FTDI reprogrammed)
F_TDIH2FTDI U4, pin 13
F_TDOG4FTDI U4, pin 14
F_TMSF4FTDI U4, pin 15
M_TCKH5JB2, pin 1004x5 Module JTAG



Bank with VCCIO is VREF_JTAG from Module



M_TDIJ2JB2, pin 96
M_TDOJ1JB2, pin 98
M_TMSH6JB2, pin 94
FMC_TCKF8J1, pin D29FMC JTAG




TRST not used



FMC_TDIM7J1, pin D30
FMC_TDON7J1, pin D31
FMC_TMSM8J1, pin D33
FMC_TRSTN8J1, pin D34
PCIE_TCKL11J3, pin A5PCIe JTAG




Currently not used




PCIE_TDIN12J3, pin A6
PCIE_TDOM12J3, pin A7
PCIE_TMSM13J3, pin A8
PCIE_TRSTG10J3, pin B9
PCIE_PERSTF12J3, pin A11Indication that PCIe Bus is up (power, clocks)
EN_FMCL4U14, pin 9Enable switched 3.3V FMC powerpulled down
EN_FMC_VADJK7U1, pin 41Enable IO power FMC_VADJpulled down
EN_PERF13Q4, pin 5Enable perepherie power 3V3_PERpulled down
FAN_FMC_ENK8Q1, pin 5Enable FMC FANfloating during configuration (no pull down)
FMC_PG_C2MM5J1, pin D1Indicate that all FMC related powers are uppulled up
FMC_PRSNT_M2C_LE9J1, pin H2Indicate if FMC installedLow when FMC present
FMC_SCLJ8J1, pin C31I2C 2-wire serial busMUX in CPLD
FMC_SDAF9J1, pin C30
PG_FMC_VADJJ6U1, pin 35Indicate FMC VADJ power is up
FF_RSTLB9J13, pin 6  and J18, pin 6Reset configurationBoth FF are resetted simultanously when pulled LOW
FFA_INTLE8J13, pin 5Indicate interrrupt

LOW when fault condition, pulled up

FFA_MPRSC10J13, pin 3Indicate FF Module installedLOW when Module present, pulled up
FFA_MSELC9J13, pin 4Select attached FF ModulePull low to use I2C
FFA_SCLD6J13, pin 8I2C 2-wire serial busMUX in CPLD
FFA_SDAE6J13, pin 7
FFB_INTLA10J18, pin 5Indicate interrruptLOW when fault condition, pulled up
FFB_MPRSA11J18, pin 3Indicate FF Module installedLOW when Module present, pulled up
FFB_MSELB10J18, pin 4Select attached FF ModulePull low to use I2C
FFB_SCLD8J18, pin 8I2C 2-wire serial busMUX in CPLD
FFB_SDAA9J18, pin 7
CPLD_IO_1B12JB1, pin 88(M)IOs from 4x5 Module(M)IOs used for ETH PHY LEDs

CPLD_IO_2A12JB1, pin 92(M)IOs from 4x5 Module
M10_RSTD1J5, pin 6


Currently not used,  functions possible with non standard CPLD firmware.


M10_RXE4J5, pin 8
M10_TXE3J5, pin 7
EN1D11JB1, pin 27Enable on module powerDepends on module, on some similar to reset.
MODEB11JB1, pin 31Boot Mode selectionFor Zynq modules only. (LOW → SD, HIGH → primary QSPI)
NOSEQE13JB1, pin 8Disable module CPLD power managementDepends on module. On some modules no extended CPLD power management avaialble.
PGOODC11JB1, pin 29Power good signal

This is only for monitoring, do not use as powerenable! Pulled up.

RESINE12JB2, pin 17Module ResetAktive LOW
M3.3VOUTM4JB2, pin 9 and 11Indicates module power is up

Used for perepherie power enable. Floating when no module installed (no pull down).

SFPA_LOSM10J12, pin 8SFP signal lossHIGH indicates signal loss
SFPA_M-DEF0F10J12, pin 6SFP modul absentHIGH when module physically absent
SFPA_RS0N10J12, pin 7SFP rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_RS1M11J12, pin 9SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_SCLL10J12, pin 5

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

System Controller CPLD MAX10

The Intel/Altera MAX10 10M08SAU169C8G System Controller CPLD (U11) is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware. It generates output signals to control the system, the on-board peripherals and the interfaces. The JTAG and I2C between the on-board peripherals and the attached module are by-passed, forwarded and controlled by the System Controller CPLD. A main tasks of the System Controller CPLD is the monitoring of the power-on sequence and configuring the state of the attached module. For detailed information, refer to the firmware documentation of the SC CPLD. Table below lists the SC CPLD I/O signals and pins:

GPIO's available to user
(FIFO or other FTDI functions when FTDI reprogrammed)
Forwarded JTAG signals from FTDI chip.
(FIFO or other FTDI functions when FTDI reprogrammed)
4x5 Module JTAG
Bank with VCCIO is VREF_JTAG from Module
FMC JTAG
TRST not used
PCIe JTAG
Currently not used
J1, pin C31
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Signal nameSC CPLD PinConnected toFunctionNotes
ACBUS0A4FTDI U4, pin 22
ACBUS1B4FTDI U4, pin 23
ACBUS2A5FTDI U4, pin 24
ACBUS3B5FTDI U4, pin 25
ACBUS4A6FTDI U4, pin 26
ACBUS5B6FTDI U4, pin 27
ACBUS6A7FTDI U4, pin 28
ACBUS7A8FTDI U4, pin 29
ADBUS4A2FTDI U4, pin 17
ADBUS5B2FTDI U4, pin 18
ADBUS6A3FTDI U4, pin 19
ADBUS7B3FTDI U4, pin 20
TCKG2FTDI U4, pin 12
TDIF5FTDI U4, pin 13
TDOF6FTDI U4, pin 14
TMSG1FTDI U4, pin 15
M_TCKH5JB2, pin 100
M_TDIJ2JB2, pin 96
M_TDOJ1JB2, pin 98
M_TMSH6JB2, pin 94
FMC_TCKF8J1, pin D29
FMC_TDIM7J1, pin D30
FMC_TDON7J1, pin D31
FMC_TMSM8J1, pin D33
FMC_TRSTN8J1, pin D34
PCIE_TCKL11J3, pin A5
PCIE_TDIN12J3, pin A6
PCIE_TDOM12J3, pin A7
PCIE_TMSM13J3, pin A8
PCIE_TRSTG10J3, pin B9
PCIE_PERSTF12J3, pin A11Indication that PCIe Bus is up (power, clocks)
EN_FMCL4U14, pin 9Enable switched 3.3V FMC powerpulled down
EN_FMC_VADJK7U1, pin 41Enable IO power FMC_VADJpulled down
EN_PERF13Q4, pin 5Enable perepherie power 3V3_PERpulled down
FAN_FMC_ENK8Q1, pin 5Enable FMC FAN
FMC_PG_C2MM5J1, pin D1Indicate that all FMC related powers are uppulled up
FMC_PRSNT_M2C_LE9J1, pin H2Indicate if FMC installedLow when FMC present
FMC_SCLJ8
I2C 2-wire serial busMUX in CPLD
FMC
SFPA_SDA
F9J1, pin C30
N9J12, pin 4
SFPA_TX_DISM9J12, pin 3SFP transmitter disableHIGH disables transmitter
SFPA_TX_FAULTG9J12, pin 2Indicates SFP laser faultHIGH indicates fault
VID0
PG
_FMC_VADJ
J6
E10U1, pin
35
34
Indicate
FMC
VADJ power is upFF_RSTLB9J13, pin 6  and J18, pin 6Reset configurationBoth FF are resetted simultanously when pulled LOWFFA_INTLE8J13, pin 5Indicate interrrupt

LOW when fault condition, pulled up

FFA_MPRSC10J13, pin 3Indicate FF Module installedLOW when Module present, pulled upFFA_MSELC9J13, pin 4Select attached FF ModulePull low to use I2CFFA_SCLD6J13, pin 8I2C 2-wire serial busMUX in CPLDFFA_SDAE6J13, pin 7FFB_INTLA10J18, pin 5Indicate interrruptLOW when fault condition, pulled upFFB_MPRSA11J18, pin 3Indicate FF Module installedLOW when Module present, pulled upFFB_MSELB10J18, pin 4Select attached FF ModulePull low to use I2CFFB_SCLD8J18, pin 8I2C 2-wire serial busMUX in CPLDFFB_SDAA9J18, pin 7CPLD_IO_1B12JB1, pin 88(M)IOs from 4x5 Module(M)IOs used for ETH PHY LEDs
CPLD_IO_2A12JB1, pin 92(M)IOs from 4x5 ModuleM10_RSTD1

TP22

Not used
M10_RXE4TP24M10_TXE3TP23EN1D11JB1, pin 27Enable on module powerDepends on module, on some similar to reset.MODEB11JB1, pin 31Boot Mode selectionFor Zynq modules only. (LOW → SD, HIGH → primary QSPI)NOSEQE13JB1, pin 8Disable module CPLD power managementDepends on module. On some modules no extended CPLD power management avaialble.PGOODC11JB1, pin 29Power good signal

This is only for monitoring, do not use as powerenable! Pulled up.

RESINE12JB2, pin 17Module ResetAktive LOWM3.3VOUTM4JB2, pin 9 and 11Indicates module power is upUsed for perepherie power enable.SFPA_LOSM10J12, pin 8SFP signal lossHIGH indicates signal lossSFPA_M-DEF0F10J12, pin 6SFP modul absentHIGH when module physically absentSFPA_RS0N10J12, pin 7SFP rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SRSFPA_RS1M11J12, pin 9SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SRSFPA_SCLL10J12, pin 5I2C 2-wire serial busMUX in CPLDSFPA_SDAN9J12, pin 4SFPA_TX_DISM9J12, pin 3SFP transmitter disableHIGH disables transmitterSFPA_TX_FAULTG9J12, pin 2Indicates SFP laser faultHIGH indicates faultVID0_FMC_VADJE10U1, pin 34FMC_VADJ Voltage selectChip internal pulled up
VID1_FMC_VADJJ7U1, pin 33VID2_FMC_VADJL5U1, pin 32VID0K6S2-1For FMC_VADJ Voltage select
VID1N5S2-2VID2N4S2-3JTAGENE5S2-4FMC_JTAGL3S2-6CM0M3S2-7CM1L2S2-8CM2K2S3-1USR0K1S3-2USB_OCD9U12, pin 5BUTTONN6S1LED1J5D1user LEDLED2K5D2-C2D4Status LEDFor further explanation see SC CPLD Firmware descriptionPHY_LED1D12J9Phy LEDs
PHY_LED1RC13J9PHY_LED2B13J9PHY_LED2RC12J9A_00_NJ10JB1, pin 38Module to CPLD communication
Currently "three wire" I2C  and RGPIO, see SC CPLD Firmware description
A_00_PK10JB1, pin 36A_01_NL12JB1, pin 35A_01_PK11JB1, pin 37A_02_NJ12JB1, pin 41A_02_PK12JB1, pin 39A_03_NH10JB1, pin 44A_03_PJ9JB1, pin 42A_04_NH13JB1, pin 47A_04_PJ13JB1, pin 45A_05_NH8JB1, pin 57A_05_PH9JB1, pin 55A_06_NG12JB1, pin 49A_06_PG13JB1, pin 51A_07L13JB1, pin 34

FTDI FT2232H

The TEF1002 board has an on-board microUSB 2.0 (J10) high-speed to JTAG/UART/FIFO IC FT2232H (U4) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed to the B2B connector. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

_VADJ Voltage selectChip internal pulled up


VID1_FMC_VADJJ7U1, pin 33
VID2_FMC_VADJL5U1, pin 32
VID0K6S2-1For FMC_VADJ Voltage select





VID1N5S2-2
VID2N4S2-3
JTAGENE5S2-4

FMC_JTAGB1S2-6Enable FMC JTAG port
CM0M3S2-7Dips for module control signals





CM1L2S2-8
CM2K2S3-1
USR0C1S3-2User buttonCurrently used for override FMC VADJ enable
USB_OCD9U12, pin 5USB overcurrent detection
EN_5VSATAE1U15, pin 1Enable SATA pin 7 power
OC_VSATAF1U15, pin 2Overcurrent detection SATA pin 7 power
BUTTONN6S1Reset button
SD-CDM1J8, pin 9SD-Card card detect switchCurrently not used
LED1J5D1User LED
LED2K5D2
-C2D4Status LEDFor further explanation see SC CPLD Firmware description
PHY_LED1D12J9Phy LEDs







PHY_LED1RC13J9
PHY_LED2B13J9
PHY_LED2RC12J9
A_00_NJ10JB1, pin 38Module to CPLD communication














Currently "three wire" I2C  and RGPIO, see SC CPLD Firmware description













A_00_PK10JB1, pin 36
A_01_NL12JB1, pin 35
A_01_PK11JB1, pin 37
A_02_NJ12JB1, pin 41
A_02_PK12JB1, pin 39
A_03_NH10JB1, pin 44
A_03_PJ9JB1, pin 42
A_04_NH13JB1, pin 47
A_04_PJ13JB1, pin 45
A_05_NH8JB1, pin 57
A_05_PH9JB1, pin 55
A_06_NG12JB1, pin 49
A_06_PG13JB1, pin 51
A_07L13JB1, pin 34


FTDI FT2232H

The TEF1002 board has an on-board microUSB 2.0 (J10) high-speed to JTAG/UART/FIFO IC FT2232H (U4) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed to the B2B connector. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.

Warning

Do not access the FT2232H EEPROM using FTDI programming tools. Doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Refer to the FTDI datasheet to get information about other options of the FT2232H chip.

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FTDI U4 pinSignal Schematic NameConnected to,  PinFunctionNotes
Pin 22ACBUS0SC CPLD U4, A4GPIO's available to user











(FIFO or other FTDI functions when FTDI reprogrammed)











Pin 23ACBUS1SC CPLD U4, B4
Pin 24ACBUS2SC CPLD U4, A5
Pin 25ACBUS3SC CPLD U4, B5
Pin 26ACBUS4SC CPLD U4, A6
Pin 27ACBUS5SC CPLD U4, B6
Pin 28ACBUS6SC CPLD U4, A7
Pin 29ACBUS7SC CPLD U4, A8
Pin 17ADBUS4SC CPLD U4, A2
Pin 18ADBUS5SC CPLD U4, B2
Pin 19ADBUS6SC CPLD U4, A3
Pin 20ADBUS7SC CPLD U4, B3
Pin 12F_TCKSC CPLD U4, H3JTAG signals forward to SC CPLD U4

(FIFO or other FTDI functions when FTDI reprogrammed)

Pin 13F_TDISC CPLD U4, H2
Pin 14F_TDOSC CPLD U4, G4
Pin 15F_TMSSC CPLD U4, F4
Pin 32BDBUS0JB1, 91UART
Pin 33BDBUS1JB1, 86


SDIO Port Expander

The TEF1002 is equipped with the Texas Instruments TXS02612 SDIO Port Expander (U3), which is used as a SDIO level shifter. Port A is connected to the  B2B connector J1. The IO Voltage VCCA_SD of this port is selected by jumper J7 and has to be set according to the module  attached. Port B0 is directly connected to the microSD Card connector (J8).

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Port Expander U3 pinSignal Schematic NameConnected to B2B  PinNotes
Pin 6SD-D0JB1, Pin 24Signals levelshiftet to 3.3V and connected to card holder (J8)
Pin 7SD-D1JB1, Pin 22
Pin 1SD-D2JB1, Pin 20
Pin 3SD-D3JB1, Pin 18
Pin 4SD-CMDJB1, Pin 26
Pin 9SD-CCLKJB1, Pin 28


Configuration DIP-switches

S2 and S3 provide 10 dip-switchs for configuration purpurses. Some of them are hard wired others are SC CPLD firmware dependent. If Firmware dependet, the functions in Notes are for the actual delivery firmware. For further descriptions see firmware descriptionRefer to the FTDI datasheet to get information about other options of the FT2232H chip.

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FTDI U4 pin
SwitchSignal Schematic NameConnected to,  Pin
Function
Notes
Pin 22
S2-1VID0
ACBUS0
SC CPLD
U4, A4GPIO's available to user
(FIFO or other FTDI functions when FTDI reprogrammed)
Pin 23ACBUS1SC CPLD U4, B4Pin 24ACBUS2SC CPLD U4, A5Pin 25ACBUS3SC CPLD U4, B5Pin 26ACBUS4SC CPLD U4, A6Pin 27ACBUS5SC CPLD U4, B6Pin 28ACBUS6SC CPLD U4, A7Pin 29ACBUS7SC CPLD U4, A8Pin 17ADBUS4SC CPLD U4, A2Pin 18ADBUS5SC CPLD U4, B2Pin 19ADBUS6SC CPLD U4, A3Pin 20ADBUS7SC CPLD U4, B3Pin 12TCKSC CPLD U4, G2JTAG signals forward to SC CPLD U4

(FIFO or other FTDI functions when FTDI reprogrammed)

Pin 13TDISC CPLD U4, F5Pin 14TDOSC CPLD U4, F6Pin 15TMSSC CPLD U4, G1Pin 32BDBUS0JB1, 91UARTPin 33BDBUS1JB1, 86

SDIO Port Expander

...

U11, K6SC CPLD firmware dependent, used for FMC_VADJ, see table below. Select according to the IO capabilites of attached 4x5 SoM and FMC.
S2-2VID1SC CPLD U11, N5
S2-3VID2SC CPLD U11, N4
S2-4JTAGENSC CPLD U11, E5ON TEF1002 SC CPLD JTAG; OFF CPLD IOs, hard wired.
S2-5M_JTAGENJB1, Pin 90When S2-6 OFF: OFF 4x5 module  FPGA/SOC JTAG, ON 4x5 module CPLD JTAG, hard wired.
S2-6FMC_JTAGSC CPLD U11, L3SC CPLD firmware dependent. ON: FMC JTAG; OFF 4x5 module JTAG, see S2-5.
S2-7

CM0

SC CPLD U11, M3SC CPLD firmware dependent, EN1
S2-8CM1SC CPLD U11, L2SC CPLD firmware dependent, NOSEQ
S3-1CM2SC CPLD U11, K2SC CPLD firmware dependent, BOOT MODE
S3-2USR0SC CPLD U11, K1SC CPLD firmware dependent, Override FMC_EN_VADJ



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Port Expander U3 pinSignal Schematic NameConnected to B2B  PinNotes
Pin 6SD-D0JB1, Pin 24Signals levelshiftet to 3.3V and connected to Card holder (J8)
Pin 7SD-D1JB1, Pin 22
Pin 1SD-D2JB1, Pin 20
Pin 3SD-D3JB1, Pin 18
Pin 4SD-CMDJB1, Pin 26
Pin 9SD-CCLKJB1, Pin 28

Configuration DIP-switches

S2-1S2-2S2-3Output Voltage
OFFOFFOFF3.3V
OFFOFFON2.5V
OFFONOFF1.8V
OFFONON1.5V
ONOFFOFF1.25V
ONOFFON1.2V
ONONOFF0.8V


Jumper

There are two voltage select jumpers available. J4 is used to select the SDIO signal voltage and J7 is used to select VCCIOA IO Voltage. Both have to be selected according to the attached 4x5 module capabilities (See TRM of your module).S2 and S3 provide 10 dip-switchs for configuration purpurses. Some of them are hard wired others are SC CPLD firmware dependent. If Firmware dependet, the functions in Notes are for the actual delivery firmware. For further descriptions see firmware description.

SC CPLD firmware dependent, Override FMC_EN_VADJ
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SwitchSignal Schematic NameConnected to,  PinNotes
S2-1VID0SC CPLD U11, K6SC CPLD firmware dependent, used for FMC_VADJ, see table below.
S2-2VID1SC CPLD U11, N5
S2-3VID2SC CPLD U11, N4
S2-4JTAGENSC CPLD U11, E5OFF TEF1002 SC CPLD JTAG; ON module/FMC JTAG, hard wired.
S2-5M_JTAGENJB1, Pin 90When S2-4 ON and S2-6 OFF: OFF 4x5 module CPLD JTAG, ON 4x5 module FPGA/SOC JTAG, hard wired.
S2-6FMC_JTAGSC CPLD U11, L3SC CPLD firmware dependent. When S2-4 ON: ON FMC JTAG; OFF 4x5 module JTAG
S2-7

CM0

SC CPLD U11, M3SC CPLD firmware dependent, EN1
S2-8CM1SC CPLD U11, L2SC CPLD firmware dependent, NOSEQ
S3-1CM2SC CPLD U11, K2SC CPLD firmware dependent, BOOT MODE
S3-2USR0SC CPLD U11, K1
JumperPower rail3.3V1.8VRemark
J4VCCIOA1-22-3Powers 4x5 bank, where FFA and FFB high speed signals are connected.
J7VCCA_SD1-22-3Powers SDIO Levelshifter on 4x5 module side.