Versions Compared

Old Version 10

changes.mady.by.user Pedram Babakhani

Saved on

compared with

New Version 11

changes.mady.by.user Pedram Babakhani

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

  1. Uninsulated 2 mm rigid socket. J8-J7
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. Box Headers, Straight/Angled J5-J16
  5. Board to Board Connector. J1...4
  6. Clock Oscillator, U2
  7. On-Board LED, D1D2...34
  8. DIP-Switch, S1...3
  9. XMOD JTAG Base, 

...

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

B2B Connector

TMSJ2-126
TDIJ2-122
TDOJ2-124
TCK

J2-120

MRJ2-83
RXDJ3-141
TXDJ3-139

...


On-board Peripherals

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

Page properties
hiddentrue
idComments
MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI

...

Notes :

  • add subsection for every component which is important for design, for example:
    • Two
Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

Scroll Title
anchorTable_OBP
titleOn board peripherals

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Chip/InterfaceDesignatorNotes

Quad SPI Flash Memory

...

hiddentrue
idComments

Notes :

...






DIP Switch

There are thre DIP Switches, S1, S2, S3.

The Boot Mode can be set through DIP Switch S1, refer to Boot Mode table.

U?? Pin
Scroll Title
anchorTable_OBP_SPIDIP
titleQuad SPI interface MIOs and pinsDIP Switch S1

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO Pin
Signals
Schematic

B2B

S1 switchNotes

...

MODE0J2-109S1A
MODE1J2-107S1B
MODE2J2-105S1C
MODE3J2-103S1D



scrolltitleanchorTableOBPI2C_RTC
Scroll Title
anchorTable_OBP_RTCDIP
titleI2C interface MIOs and pinsDIP Switch S2

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinSignalsSchematicB2BS2 switchU? PinNotes
EN_PSGT
J2-
84
S2A

EN_
GT_
titleI2C Address for RTC
Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
stylewidths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
MIO PinI2C AddressDesignatorNotes

...

RJ2-95S2B
EN_GT_LJ2-97S2C
EN_PLL_PWRJ2-77S2Dconnected to PG_PL



Notes
Scroll Title
anchorTable_OBP_EEPDIP
titleI2C EEPROM interface MIOs and pinsDIP Switch S3

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO Pin
SignalsSchematicB2BS3 switchU?? PinNotes
Scroll Title
anchorTable_OBP_I2C_EEPROM
titleI2C address for EEPROM
EN_DDRJ2-112S3A
EN_LPDJ2-108S3B
EN_PLJ2-101S3C
EN_FPDJ2-102S3D
Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
stylewidths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
MIO PinI2C AddressDesignator


LEDs

Scroll Title
anchorTable_OBP_LED
titleOn-board LEDs

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicDesignatorColorConnected toActive LevelNote

DDR3 SDRAM

Page properties
hiddentrue
idComments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

...

D2RedDONELow
D3RedERR_STATUSLow
D4RedERR_OUTLow

...




Ethernet

Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

BankSignal NameETH1ETH2Signal Description







































































...

Scroll Title
anchorTable_OBP_CLK
titleOsillators

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorDescriptionFrequencyNote
U2MHzMEMS Oscillator125.00 MHzKHz


Power and Power-On Sequence

...