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Template Revision 2.1 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Template Revision 1.0
Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
Scroll pdf ignore

Table of contents

Table of Contents
outlinetrue

Overview

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General Design description
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Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

Key Features

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Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • SI5338 Initialisation with FSBL (optional)
  • Special FSBL for QSPI Programming

Revision History

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- Add changes from design
- Export PDF to download, if vivado revision is changed!
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...

  • new assembly variant

...

  • Board Part Bug fix with UART 1

...

  • No Design changes
  • Add FSBL for Flash Programming

...

  • New Web Link on Board Part Files
  • Add optional FSBL Code to reprogram  SI5338

...

  • changed Flash typ on TE0715_board_files.csv
    (older one is not supported on Vivado 2017.2)

...

  • initial release

Release Notes and Know Issues

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...

Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

TE0715-04-30-1IA

...

Design supports following carriers:

...

Additional HW Requirements:

...

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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Only on ZIP file with Prebuilt content.

...

File

...

File-Extension

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Description

...

BIF-File

...

*.bif

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File with description to generate Bin-File

...

BIN-File

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*.bin

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Flash Configuration File with Boot-Image (Zynq-FPGAs)

...

BIT-File

...

*.bit

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FPGA (PL Part) Configuration File

...

DebugProbes-File

...

*.ltx

...

Definition File for Vivado/Vivado Labtools Debugging Interface

...

Diverse Reports

...

---

...

Report files in different formats

...

Hardware-Platform-Specification-Files

...

*.hdf

...

Exported Vivado Hardware Specification for SDK/HSI and PetaLinux

...

LabTools Project-File

...

*.lpr

...

Vivado Labtools Project File

...

OS-Image

...

*.ub

...

Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

...

Software-Application-File

...

*.elf

...

Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText
        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use

        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12
  • ...
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Table of contents

Table of Contents
outlinetrue

Overview

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Notes :

Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

Refer to http://trenz.org/te0715-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design
Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • SI5338 Initialisation with FSBL (optional)
  • Special FSBL for QSPI Programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description



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DateVivadoProject BuiltAuthorsDescription
2018-10-012018.2TE0715-test_board-vivado_2018.2-build_03_20181001131411.zip
TE0715-test_board_noprebuilt-vivado_2018.2-build_03_20181001131421.zip
John Hartfiel
  • Rework Board Part Files (PS)
  • small design changes
  • SI5338 reconfiguration default activated on FSBL
  • update linux startup app
2018-04-262017.4TE0715-test_board-vivado_2017.4-build_07_20180426171530.zip
TE0715-test_board_noprebuilt-vivado_2017.4-build_07_20180426171546.zip
John Hartfiel
  • new assembly variant
2018-03-272017.4te0715-test_board-vivado_2017.4-build_07_20180327223552.zip
te0715-test_board_noprebuilt-vivado_2017.4-build_07_20180327223606.zip
John Hartfiel
  • Board Part Bug fix with UART 1
2018-01-052017.4te0715-test_board-vivado_2017.4-build_01_20180105195436.zip
te0715-test_board_noprebuilt-vivado_2017.4-build_01_20180105195452.zip
John Hartfiel
  • No Design changes
  • Add FSBL for Flash Programming
2017-11-102017.2te0715-test_board-vivado_2017.2-build_05_20171110134232.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_05_20171110134247.zip
John Hartfiel
  • New Web Link on Board Part Files
  • Add optional FSBL Code to reprogram  SI5338
2017-10-192017.2te0715-test_board-vivado_2017.2-build_04_20171019141808.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_04_20171019141825.zip
John Hartfiel
  • changed Flash typ on TE0715_board_files.csv
    (older one is not supported on Vivado 2017.2)
2017-09-222017.2te0715-test_board-vivado_2017.2-build_02_20170927143412.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_02_20170927143427.zip
John Hartfiel
  • initial release

Release Notes and Know Issues

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  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed
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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
Timing problems with Frequency countercan be ignored---with 2018-10-01 update

Requirements

Software

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Notes :

  • list of software which was used to generate the design



Scroll Title
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titleSoftware

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SoftwareVersionNote
Vivado2018.2needed
SDK2018.2needed
PetaLinux2018.2needed
SI5338 Clock Builder---optional

Hardware

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Notes :

  • list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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titleHardware Modules

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0715-03-15-1C03_15_1cREV01,02,031GB32

TE0715-03-15-1I03_15_1iREV01,02,031GB32

TE0715-03-15-2I03_15_2iREV01,02,031GB32

TE0715-03-30-1C03_30_1cREV01,02,031GB32

TE0715-03-30-1I03_30_1iREV01,02,031GB32

TE0715-03-30-3E03_30_3eREV01,02,031GB32

TE0715-04-15-1C04_15_1cREV041GB_L32

TE0715-04-15-1I04_15_1iREV041GB_L32

TE0715-04-15-1I304_15_1iREV041GB_L32
2,5 mm B2B connector
TE0715-04-15-2I04_15_2iREV041GB_L32

TE0715-04-30-1C04_30_1cREV041GB_L32

TE0715-04-30-1I04_30_1iREV041GB_L32

TE0715-04-30-1I304_30_1iREV041GB_L32
2,5 mm B2B connector
TE0715-04-30-3E04_30_3eREV041GB_L32

TE0715-04-12s-1C12s     REV041GB_L32

TE0715-04-30-1IA

04_30_1iREV041GB_L32
Micron instead of Spansion Flash


Design supports following carriers:

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titleHardware Carrier

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Carrier ModelNotes
TE0701
TE0703used as reference carrier 
TE0705
TE0706
TEBA0841

Additional HW Requirements:

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titleAdditional Hardware

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Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI

Content

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Notes :

  • content of the zip file


For general structure and of the reference design, see Project Delivery

Design Sources

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titleDesign sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

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TypeLocationNotes
SI5338<design name>/misc/Si5338SI5345 Project with current PLL Configuration

Prebuilt

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  • prebuilt files
  • Template Table:
    • Scroll Title
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      titlePrebuilt files

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems



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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.


Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Added
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

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Note:
  • Programming and Startup procedure
Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

TE0715-0x-30-xx  only: HP IO Banks max power supply voltage is 1.8V.

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC

...

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

...

  1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
    Note: Select correct one, see TE Board Part Files

...

  1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
    Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder

...

  1. HDF is exported to "prebuilt\hardware\<short name>"
    Note: HW Export from Vivado GUI create another path as default workspace.
  2. Create Linux images on VM, see PetaLinux KICKstart
    1. Use TE Template from /os/petalinux
      Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.

...

  1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
    Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"

...

Launch

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Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first lunch.

TE0715-0x-30-xx  only: HP IO Banks max power supply voltage is 1.8V.

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
  4. Copy image.ub on SD-Card
  5. Insert SD-Card

SD

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 1 Bus type: i2cdetect -y -r 1
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc

Vivado HW Manager 

MGT Reference CLK Counter: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz

MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible see FSBL description).

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System Design - Vivado

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Block Design

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PS Interfaces

Activated interfaces:

...

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
Code Block
languageruby
title_i_unused_io.xdc
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Code Block
languageruby
title_i_io.xdc
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

Application

zynq_fsbl

TE modified 2017.4 FSBL

Changes:

  • Si5338 Configuration see fsbl_hooks.c
    add define RECONFIGURE_SI5338 to enable PLL programming with given register_map.h setup
  • Add register_map.h, si5338.c, si5338.h

zynq_fsbl_flash

TE modified 2017.4 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

No changes.

Device Tree

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languagejs

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-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0715" possible
  4. Copy image.ub on SD-Card
  5. Insert SD-Card

SD

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 1 Bus type: i2cdetect -y -r 1
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc

Vivado HW Manager 

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

CLK Counters: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
    2. MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible over FSBL, see FSBL description).
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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...


Block Design

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PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

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TypeNote
DDR---
QSPIMIO
I2C1MIO
UART0MIO
GPIOMIO
ETH, USB RstMIO
SD0MIO
USB0MIO
ETH0MIO
TTC0..1EMIO
WDTEMIO

Constrains

Basic module constrains

Code Block
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title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
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title_i_unused_io.xdc
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Code Block
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title_i_io.xdc
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]
Code Block
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title_i_timing.xdc
# for fmeter only
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_1/U0/BUFG_O[0]}]

Software Design - SDK/HSI

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Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Application

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2018.2 FSBL

Changes:

  • Si5338 Configuration
    • see main.c, fsbl_hooks.c (d/remove define RECONFIGURE_SI5338 to enable PLL programming with given register_map.h setup (default activate))
    • Add register_map.h, si5338.c, si5338.h

zynq_fsbl_flash

TE modified 2018.2 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0715

Hello TE0715 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

No changes.

Device Tree

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/include/ "system-conf.dtsi"
/ {
};


/* default */

/* ETH PHY */
&gem0 {

    status = "okay";
        ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
                reg = <0>;
    };
};


/* USB PHY */
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        ethernet_phy0: ethernet-phy@0 {//compatible = "usb-nop-xceiv";
        compatible#phy-cells = "marvell,88e1510"<0>;
        device_typereg = "ethernet-phy" <0xe0002000 0x1000>;
        view-port = <0x0170>;
      reg = <0>drv-vbus;
    };
};


/* USB PHY */
/&usb0 {
    usb_phy0: usb_phy@0 {
        compatibledr_mode = "ulpi-phyhost";
        //compatibledr_mode = "usb-nop-xceivperipheral";
        #phy-cellsusb-phy = <0>;
        reg = <0xe0002000 0x1000>;<&usb_phy0>;
};

/* I2C */
// i2c PLL: 0x70, i2c eeprom: 0x50

&i2c1 {
    rtc@6F {   view-port = <0x0170>;
   // Real    drv-vbus;Time Clock
    };
};

&usb0 {
  compatible  dr_mode = "hostisl12022";
    //dr_mode   reg = "peripheral"<0x6F>;
    usb-phy = <&usb_phy0>;
};

/* I2C */
// i2c PLL: 0x70, i2c eeprom: 0x50

&i2c1 {
    rtc@6F {        // Real Time Clock
       compatible = "isl12022";
       reg = <0x6F>;
   };

};


Kernel

Activate:

  • RTC_DRV_ISL12022

Rootfs

Activate:

  • i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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SI5338

Download  ClockBuilder Desktop for SI5338

  1. Install and start ClockBuilder
  2. Select SI5338
  3. Options → Open register map file
    Note: File location <design name>/misc/Si5338/RegisterMap.txt
  4. Modify settings
  5. Options → save C code header files
  6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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  • New assembly variant

...

};

};



Kernel

Activate:

  • RTC_DRV_ISL12022

Rootfs

Activate:

  • i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:


SI5338

File location <design name>/misc/Si5338/RegisterMap.txt

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports
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DateDocument Revision

Authors

Description
Page info
modified-date
modified-date
dateFormatyyyy-MM-dd


Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat


Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Release 2018.2
  • Redesign Board Part Files
  • New activate SI5338 example over FSBL
  • small Design changes
  • Update Documentation Style
  • Release 2018.2
  • Redesign Board Part Files
  • New activate SI5338 example over FSBL
  • small Design changes
  • Update Documentation Style
  • Update in process and will be available soon



v.30John Hartfiel
  • New assembly variant

2018-03-27

v.29John Hartfiel
  • Bugfix Board Part Files
2018-02-13v.28John Hartfiel
  • Release 2017.4
2017-11-10v.22John Hartfiel
  • Design Update with new options
  • Add Si5338 section
  • Update FSBL section
2017-10-19

v.21

John Hartfiel
  • Download Update
2017-10-19v.20John Hartfiel
  • Document style update
2017-10-06v.18John Hartfiel
  • Text correction
  • Update Launch section
  • Supported PCBs
2017-10-02v.14John Hartfiel
  • Document update on Prebuilt section
2017-09-28
v.13
John Hartfiel
  • Initial Release 2017.2

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Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

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