Page History

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Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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General Design description
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Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

Key Features

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Revision History

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• new assembly variant

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• Board Part Bug fix with UART 1

...

• No Design changes
• Add FSBL for Flash Programming

...

• New Web Link on Board Part Files
• Add optional FSBL Code to reprogram  SI5338

...

• changed Flash typ on TE0715_board_files.csv
  (older one is not supported on Vivado 2017.2)

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• initial release

Release Notes and Know Issues

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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TE0715-04-30-1IA

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Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Overview

Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

Refer to http://trenz.org/te0715-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0715 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported HDF
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. Generate Programming Files with HSI/SDK
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
      
      

Launch

Additional Sources

...

Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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Only on ZIP file with Prebuilt content.

...

File

...

File-Extension

...

Description

...

BIF-File

...

*.bif

...

File with description to generate Bin-File

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BIN-File

...

*.bin

...

Flash Configuration File with Boot-Image (Zynq-FPGAs)

...

BIT-File

...

*.bit

...

FPGA (PL Part) Configuration File

...

DebugProbes-File

...

*.ltx

...

Definition File for Vivado/Vivado Labtools Debugging Interface

...

Diverse Reports

...

---

...

Report files in different formats

...

Hardware-Platform-Specification-Files

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*.hdf

...

Exported Vivado Hardware Specification for SDK/HSI and PetaLinux

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LabTools Project-File

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*.lpr

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Vivado Labtools Project File

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OS-Image

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*.ub

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Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

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Software-Application-File

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*.elf

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Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

• TE0715 "Test Board" Reference Design

Design Flow

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Basic Design Steps
Add/ Remove project specific 
  -->

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC

...

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

...

1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
   Note: Select correct one, see TE Board Part Files

...

1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
   Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder

...

1. HDF is exported to "prebuilt\hardware\<short name>"
   Note: HW Export from Vivado GUI create another path as default workspace.
2. Create Linux images on VM, see PetaLinux KICKstart
   1. Use TE Template from /os/petalinux
      Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.

...

1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
   Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"

-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
            optional "TE::pr_program_flash_binfile -swapp hello_te0715" possible
4. Copy image.ub on SD-Card
5. Insert SD-Card

SD

1. Copy image.ub and Boot.bin on SD-Card.
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 1 Bus type: i2cdetect -y -r 1
   2. RTC check: dmesg | grep rtc
   3. ETH0 works with udhcpc

Vivado HW Manager 

CLK Counters: 

1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
   1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
   2. MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible over FSBL, see FSBL description).

Scroll Title
anchor Figure_VHM title Vivado Hardware Manager
Image Added

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title Block Design
Image Added

PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

# for fmeter only
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_1/U0/BUFG_O[0]}]

Software Design - SDK/HSI

For SDK project creation, follow instructions from:

• SDK Projects

Application

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2018.2 FSBL

Changes:

• Si5338 Configuration
  • see main.c, fsbl_hooks.c (d/remove define RECONFIGURE_SI5338 to enable PLL programming with given register_map.h setup (default activate))
  • Add register_map.h, si5338.c, si5338.h

zynq_fsbl_flash

TE modified 2018.2 FSBL

Changes:

• Set FSBL Boot Mode to JTAG
• Disable Memory initialisation

hello_te0715

Hello TE0715 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

<!--
- optional chapter, if petalinux is used
- Add changes from default petalinux project
   -->

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};


/* default */

/* ETH PHY */
&gem0 {

    status = "okay";
        ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
                reg = <0>;
    };
};


/* USB PHY */
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy

...

Launch

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Description of Block Design, Constrains...
BD Pictures from Export...
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Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
4. Copy image.ub on SD-Card
5. Insert SD-Card

SD

1. Copy image.ub and Boot.bin on SD-Card.
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 1 Bus type: i2cdetect -y -r 1
   2. RTC check: dmesg | grep rtc
   3. ETH0 works with udhcpc

Vivado HW Manager 

MGT Reference CLK Counter: 

1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
   1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
      

MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible see FSBL description).

Image Removed

System Design - Vivado

<!--
Description of Block Design, Constrains...
BD Pictures from Export...
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Block Design

Image Removed

PS Interfaces

Activated interfaces:

...

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - SDK/HSI

<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

• SDK Projects

Application

zynq_fsbl

TE modified 2017.4 FSBL

Changes:

• Si5338 Configuration see fsbl_hooks.c
  add define RECONFIGURE_SI5338 to enable PLL programming with given register_map.h setup
• Add register_map.h, si5338.c, si5338.h

zynq_fsbl_flash

TE modified 2017.4 FSBL

Changes:

• Set FSBL Boot Mode to JTAG
• Disable Memory initialisation

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

<!--
- optional chapter, if petalinux is used
- Add changes from default petalinux project
   -->

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};


/* default */

/* ETH PHY */
&gem0 {

    status = "okay";
        ethernet_phy0: ethernet-phy@0 {//compatible = "usb-nop-xceiv";
        compatible#phy-cells = "marvell,88e1510"<0>;
        device_typereg = "ethernet-phy" <0xe0002000 0x1000>;
        view-port = <0x0170>;
      reg = <0>drv-vbus;
    };
};


/* USB PHY */
/&usb0 {
    usb_phy0: usb_phy@0 {
        compatibledr_mode = "ulpi-phyhost";
        //compatibledr_mode = "usb-nop-xceivperipheral";
        #phy-cellsusb-phy = <0>;
        reg = <0xe0002000 0x1000>;<&usb_phy0>;
};

/* I2C */
// i2c PLL: 0x70, i2c eeprom: 0x50

&i2c1 {
    rtc@6F {   view-port = <0x0170>;
   // Real    drv-vbus;Time Clock
    };
};

&usb0 {
  compatible  dr_mode = "hostisl12022";
    //dr_mode   reg = "peripheral"<0x6F>;
    usb-phy = <&usb_phy0>;
};

/* I2C */
// i2c PLL: 0x70, i2c eeprom: 0x50

&i2c1 {
    rtc@6F {        // Real Time Clock
       compatible = "isl12022";
       reg = <0x6F>;
   };

};

Kernel

Activate:

• RTC_DRV_ISL12022

Rootfs

Activate:

• i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

SI5338

Download  ClockBuilder Desktop for SI5338

1. Install and start ClockBuilder
2. Select SI5338
3. Options → Open register map file
   Note: File location <design name>/misc/Si5338/RegisterMap.txt
4. Modify settings
5. Options → save C code header files
6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
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...

• New assembly variant

};

};

Kernel

Activate:

• RTC_DRV_ISL12022

Rootfs

Activate:

• i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

SI5338

File location <design name>/misc/Si5338/RegisterMap.txt

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

...

v.13

...

...

...

...

...

...

Legal Notices

...