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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0006 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramName | TEI0006_OV_BD |
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| simpleViewer | false |
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| links | auto |
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| tbstyle | hidden |
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| lbox | true |
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| diagramWidth | 638 |
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| revision | 1113 |
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| Scroll Only |
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Main Components
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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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| Intel Cyclone 10 GX | 1C | J3 | 24 Single ended (12 Diff pair) | 0.95V |
| 1D | J3 | 24 Single ended (12 Diff pair) | 0.95V |
| | 2A | J2 | 1 Single ended | 1.8V | PERST | | 2J | J2 | 46 Single ended (23 Diff pair) | 1.8V |
| | 2K | J1 | 46 Single ended (23 Diff pair) | VCCIO2K |
| | 2L | J1 | 46 Single ended (23 Diff pair) | 3.0V |
| | 3A | - | - | 1.35V | VDD_DDR | | 3B | - | - | 1.35V | VDD_DDR | | Intel Max 10 | 1A | J2 | 8 Single ended | 3.3V |
| | 1B | J2 | 5 Single ended | 3.3V |
| | 2 | J3 | 2 Single ended | 1.8VIO |
| | 3 | - | - | 1.8VIO |
| | 5 | J2 | 4 Single ended | 3.3V |
| | 6 | J2 | 2 Single ended | 3.3V |
| | 8 | J2 | 25 Single ended | 3.3V |
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JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMX.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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JTAG access to the TExxxx SoM through B2B connector JMX.
| Scroll Title |
|---|
| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector |
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| TMS | J2-160 | | TDI | J2-159 | | TDO | J2-158 | | TCK | J2-157 | | JTAG_EN | J2-105 |
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MIO Pins
| Page properties |
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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