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- Overview of Boot Mode, Reset, Enables.
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The TEI00006 module can be configured using different modes. Mode selection can be done using MSEL[2:0]. MSEL2 is potentially connected to GND so mode selection can be done using MSEL[1:0] which are connected to Bank 3 of Intel Max 10.
| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE Signal State | MSEL2 | MSEL1 | MSEL0 | Boot Mode |
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MSEL[2:0] | 0 | 1 | 0 | AS x4 / Fast | | 0 | 1 | 1 | AS x1 / Standard | | 0 | 0 | 0 | PS and FPP/ Fast | | 0 | 0 | 1 | PS and FPP/ Standard |
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| Scroll Title |
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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| Intel Cyclone 10 GX | Bank 1C | J3 | 24 Single ended (12 Diff pair) | 0.95V |
| Bank 1D | J3 | 24 Single ended (12 Diff pair) | 0.95V |
| | Bank 2A | J2 | 1 Single ended | 1.8V | PERST | | Bank 2J | J2 | 46 Single ended (23 Diff pair) | 1.8V |
| | Bank 2K | J1 | 46 Single ended (23 Diff pair) | VCCIO2K |
| | Bank 2L | J1 | 46 Single ended (23 Diff pair) | 3.0V |
| | Bank 3A | - | - | 1.35V | VDD_DDR | | Bank 3B | - | - | 1.35V | VDD_DDR | | Intel Max 10 | Bank 1A | J2 | 8 Single ended | 3.3V |
| | Bank 1B | J2 | 5 Single ended | 3.3V |
| | Bank 2 | J3 | 2 Single ended | 1.8VIO |
| | Bank 3 | - | - | 1.8VIO |
| | Bank 5 | J2 | 4 Single ended | 3.3V |
| | Bank 6 | J2 | 2 Single ended | 3.3V |
| | Bank 8 | J2 | 25 Single ended | 3.3V |
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JTAG Interface
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.
| Scroll Title |
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| anchor | Table_OBP_RTCSPI |
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| title | I2C Quad SPI interface MIOs and pins |
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| | Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U? Pin | Notes |
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| Scroll Title |
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| anchor | Table_OBP_I2C_RTC |
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| title | I2C Address for RTCpins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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EEPROM
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? U64 Pin | B2B | Notes |
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| I2C_SCL | SCL | J3-135 | Connected to Bank 2 of Intel Max 10 | | I2C_SDA | SDA | J3-137 | Connected to Bank 2 of Intel Max 10 |
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO PinPins | I2C Address | Designator | Notes | Designator | Notes |
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| I2C_SCL, I2C_SDA | 0x53 | U64 |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Schematic| Designator | Color | Connected to | Active Level | Note |
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| D1 | Red | LED_FP_1 | Active high |
| | D2 | Green | LED_FP_2 | Active high |
| | D3 | Green | LED_FP_3 | Active high |
| | D4 | Green | LED_FP_4 | Active high |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? TEI0006 SoM has ??? GByte two 1 Gb volatile DDR3 SDRAM IC for storing user application code and data.
- Part number: IS43TR16512BL
- Supply voltage: 1.35V
- Speed: 800MHz
- NOR Flash
- Temperature:
Ethernet
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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Ethernet
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Scroll Title |
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| anchor | Table_OBP_CANETH |
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| title | CAN Tranciever interface MIOsEthernet PHY to Zynq SoC connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | U?? Pin | Notes | D-Tx | Driver Input | R-Rx | Reciever Output | | Signal Name | ETH1 | ETH2 | Signal Description |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Description | Frequency | Note |
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| U21 | MEMS Oscillator | 25MHz |
| | U15 | MEMS Oscillator | 25MHz |
| | U17 | MEMS Oscillator | 48MHz |
| | U14 | Programmable Oscillator | Variable | MHz | MHz | KHz |
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Power and Power-On Sequence
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