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title	Boot process.

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MODE Signal State	MSEL1	MSEL0	Boot Mode
MSEL[2:0]	1	0	AS x4 / Fast
	1	1	AS x1 / Standard
	0	0	PS and FPP/ Fast
	0	1	PS and FPP/ Standard

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Signal

B2BI/ONote

Signals, Interfaces and Pins

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Notes :

For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

By tying the CONF_DONE, nSTATUS, and nCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.

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title	Configuration signals.

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title	General PL I/O to B2B connectors information

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FPGA

Signals

FPGA Bank

B2B Connector

I/O Signal Count

Voltage Level

Notes

Intel Cyclone 10 GX

Bank 1C

J3

24 Single ended (12 Diff pair)

0.95V

Bank 1D

J3

24 Single ended (12 Diff pair)

0.95V

Bank 2A

J2

1 Single ended

1.8V

PERST

Bank 2J

J2

46 Single ended (23 Diff pair)

1.8V

Bank 2K

J1

46 Single ended (23 Diff pair)

VCCIO2K

Bank 2L

J1

46 Single ended (23 Diff pair)

3.0V

Bank 3A

-

1.35V

VDD_DDR

Bank 3B

-

1.35V

VDD_DDR

Intel Max 10

Bank 1A

J2

8 Single ended

3.3V

Bank 1B

J2

5 Single ended

3.3V

Bank 2

J3

2 Single ended

1.8VIO

Bank 3

-

1.8VIO

Bank 5

J2

4 Single ended

3.3V

Bank 6

J2

2 Single ended

3.3V

Bank 8

J2

25 Single ended

3.3V

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JTAG access to the TExxxx SoM through B2B connector JMX.

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title	JTAG pins connection

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JTAG Signal

...

B2B Connector

...

J2-157

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MIO Pins

...

hidden	true
id	Comments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

Connected to	Description	Note
nCONFIG	1.8V	Configuration trigger	From U18( Intel MAX 10) - Bank 3
CONF_DONE	1.8V	Configuration done	To U18( Intel MAX 10) - Bank 3
nSTATUS	1.8V	Configuration status	To U18( Intel MAX 10) - Bank 3
DCLK	U1,U3	Configuration clock	To U1(Flash Memory) From U18( Intel MAX 10) - Bank 3
AS_DATA0...3	U1	Configuration data	To U1(Flash Memory)

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Signal	B2B	Connected to	Note
PERST	J2-99	Bank A2

Signals, Interfaces and Pins

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hidden	true
id	Comments

Notes :

For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA	FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
Intel Cyclone 10 GX	Bank 1C	J3	24 Single ended (12 Diff pair)	0.95V
	Bank 1D	J3	24 Single ended (12 Diff pair)	0.95V
	Bank 2A	J2	1 Single ended	1.8V	PERST
	Bank 2J	J2	46 Single ended (23 Diff pair)	1.8V
	Bank 2K	J1	46 Single ended (23 Diff pair)	VCCIO2K
	Bank 2L	J1	46 Single ended (23 Diff pair)	3.0V
	Bank 3A	-	-	1.35V	VDD_DDR
	Bank 3B	-	-	1.35V	VDD_DDR
Intel Max 10	Bank 1A	J2	8 Single ended	3.3V
	Bank 1B	J2	5 Single ended	3.3V
	Bank 2	J3	2 Single ended	1.8VIO
	Bank 3	-	-	1.8VIO
	Bank 5	J2	4 Single ended	3.3V
	Bank 6	J2	2 Single ended	3.3V
	Bank 8	J2	25 Single ended	3.3V

JTAG Interface

JTAG access to the TEI0006 SoM through B2B connector JM2.

...

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

...

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...

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Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

...

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Notes :

...

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Chip/Interface

Designator

Notes

SDRAM DDR3 Memory, U12...13

U12...13

EEPROM

U64

SPI Flash Memory

U1- U3

Ethernet Tranciever

U2- U14

Intel® Max 10

U18

User LEDs

D1...4

D1 (Red), D2...4 (Green)

Quad SPI Flash Memory

JTAG Signal	B2B Connector	Note
TMS	J2-160
TDI	J2-159
TDO	J2-158
TCK	J2-157
JTAG_EN	J2-105	Connected to 3.3V

MIO Pins

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id	Comments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO Pin

Connected to

B2B

Notes

MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2

QSPI

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MIO Pin	Connected to	B2B	Notes

On-board Peripherals

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Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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Chip/Interface	Designator	Notes
SDRAM DDR3 Memory, U12...13	U12...13
EEPROM	U64
SPI Flash Memory	U1- U3
Ethernet Tranciever	U2- U14
Intel® Max 10	U18
User LEDs	D1...4	D1 (Red), D2...4 (Green)

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Notes

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Designator	Schematic	Connected to	Notes
U1	NCSO	CSS Bank (Configuration Bank)	Used when you are not configuring using AS
	DCK	DCLK	AS Configuration Clock
	AS_DATA0	CSS Bank (Configuration Bank)	AS Configuration Pin
	AS_DATA1	CSS Bank (Configuration Bank)	AS Configuration Data
	AS_DATA2	CSS Bank (Configuration Bank)	AS Configuration Data
	AS_DATA3	CSS Bank (Configuration Bank)	AS Configuration Data
U3	QSPI_CS	Bank 2A
	QSPI_CK	Bank 2A
	QSPI_DATA0	Bank 2A
	QSPI_DATA1	Bank 2A
	QSPI_DATA2	Bank 2A
	QSPI_DATA3	Bank 2A

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MIO Pin

Schematic

U?? Pin

Trenz Electronic Documentation

Versions Compared

Old Version 28

New Version 29

Key

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

MIO Pins

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

JTAG Interface

Quad SPI Flash Memory

MIO Pins

On-board Peripherals

Quad SPI Flash Memory

EEPROM

DDR3 SDRAM