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Template Revision 27

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
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        titleText

        Scroll Table Layout
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        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

Overview

The Trenz Electronic TEI0006 is an Industrial grade module based on Intel® Cyclone 10 GX. Intel Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation of low cost FPGAs.

Refer to http://trenz.org/tei0006-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Intel® Cyclone 10 GX Industrial [10CX220YF780I5G]
    • Package: FBGA-780
    • Speed Grade: 5 (Fastest)
    • Temperature: -40°C ~ 100°C
    • Package compatible device 10CX150 and 10CX105 as assembly variant on request possible
  • 2x SDRAM DDR3L Memory IC 8Gb, 800MHz 
  • 2x SPI Flash, 1 Gb
  • 2x Transceiver Full Ethernet 64-QFN 
  • Programmable Oscillator
  • Intel® MAX 10 as System Controller (CPLD)
  • 2Kb EEPROM Memory
  • 4x User LED 

  • I/O interfaces:
    • 284 GPIO
    • 118 LVDS
    • 12 XCVR
  • Board to Board (B2B):

    • Plug-on module with 3 x 160-pin Samtec Razor Beam (ST5) connectors
  • Power Supply:

    • 5V

  • Dimension: 80m x 60m

Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titleTEI0006 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_OV_BD
titleTEI0006 main components


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  1. Intel® MAX 10, U18
  2. DC/DC convertor, U4...11
  3. SDRAM DDR3 Memory, U12...13
  4. User LEDs, D1...4
  5. Ethernet Tranciever, U2- U14
  6. SPI Flash Memory, U1- U3
  7. Intel® Cyclone 10 GX, U23
  8. EEPROM, U64
  9. Buffer, U16

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Scroll Title
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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


EEPROMProgrammed

Programmable Oscillator configuration

DDR3 SDRAMNot Programmed



Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

The TEI0006 module can be configured using different modes. Mode selection can be done using MSEL[2:0]. MSEL2 is potentially connected to GND so mode selection can be done using MSEL[1:0] which are connected to Bank 3 of Intel Max 10.

Scroll Title
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titleBoot process.

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MODE Signal State

MSEL2MSEL1MSEL0Boot Mode

MSEL[2:0]

010

AS x4 / Fast

011

AS x1 / Standard

000PS and FPP/ Fast
001PS and FPP/ Standard


By tying the CONF_DONE, nSTATUS, and nCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.

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titleConfiguration signals.

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SignalsConnected toDescriptionNote
nCONFIG1.8VConfiguration triggerFrom U18( Intel MAX 10) - Bank 3
CONF_DONE1.8VConfiguration done To U18( Intel MAX 10) - Bank 3
nSTATUS1.8VConfiguration status To U18( Intel MAX 10) - Bank 3
DCLKU1,U3Configuration clock 

To U1(Flash Memory)

From U18( Intel MAX 10) - Bank 3

AS_DATA0...3U1Configuration dataFrom U1(Flash Memory)



Scroll Title
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titleReset process.

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Signal

B2BConnected toNote

PERST

J2-99Bank A2


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
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titleGeneral PL I/O to B2B connectors information

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FPGAFPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes

Intel Cyclone 10 GX

Bank 1C

J3

24 Single ended (12 Diff pair)

0.95V

GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P

Bank 1D

J3

24 Single ended (12 Diff pair)

0.95V

GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P

Bank 2A

J2

2 Single ended

1.8V

PERST, CLKUSR

Bank 2J

J2

46 Single ended (23 Diff pair)

1.8V


Bank 2K

J1

46 Single ended (23 Diff pair)

VCCIO2K


Bank 2L

J1

46 Single ended (23 Diff pair)

3.0V


Bank 3A

-

-

1.35V

VDD_DDR

Bank 3B

-

-

1.35V

VDD_DDR

Intel Max 10

Bank 1A

J2

8 Single ended

3.3V


Bank 1B

J2

5 Single ended

3.3V


Bank 2

J3

2 Single ended

1.8VIO


Bank 3

-

-

1.8VIO


Bank 5

J2

4 Single ended

3.3V


Bank 6

J2

2 Single ended

3.3V


Bank 8

J2

25 Single ended

3.3V




JTAG Interface

JTAG access to the TEI0006 SoM through B2B connector JM2. JTAGEN is connected to 3.3V and after power on JTAG will be enabled.

Scroll Title
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titleJTAG pins connection

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JTAG Signal

B2B Connector

Note
TMSJ2-160
TDIJ2-159
TDOJ2-158
TCK

J2-157


JTAGENJ2-105Connected to 3.3V


MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



Scroll Title
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titleMIOs pins

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MIO PinConnected toB2BNotes
MAX_IO1...22U18( Intel MAX 10) - Bank 8J2
MAX_IO23...26U18( Intel MAX 10) - Bank 8J2



On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Scroll Title
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titleOn board peripherals

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Chip/InterfaceDesignatorNotes

QSPI Flash Memory

U1- U3U1- AS configuration
EEPROMU64
DDR3 SDRAM MemoryU12...13
Ethernet PHYU2- U14
Intel Max 10U18System controller

User LEDs

D1...4D1 (Red), D2...4 (Green)
OscillatorsU14, U15, U17, U21


QSPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Scroll Title
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titleQuad SPI interface MIOs and pins

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DesignatorSchematicConnected toNotes
U1



NCSOCSS Bank (Configuration Bank)Used when you are not configuring using AS
DCKDCLKAS Configuration Clock
AS_DATA0CSS Bank (Configuration Bank)AS Configuration Pin
AS_DATA1CSS Bank (Configuration Bank)AS Configuration Data
AS_DATA2CSS Bank (Configuration Bank)AS Configuration Data
AS_DATA3CSS Bank (Configuration Bank)AS Configuration Data
U3QSPI_CSBank 2A
QSPI_CKBank 2A
QSPI_DATA0Bank 2A
QSPI_DATA1Bank 2A
QSPI_DATA2Bank 2A
QSPI_DATA3Bank 2A


EEPROM

Scroll Title
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titleI2C EEPROM interface MIOs and pins

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SchematicU64 PinB2BNotes
I2C_SCLSCLJ3-135Connected to Intel Max 10 (U18)- Bank 2
I2C_SDASDAJ3-137Connected to Intel Max 10 (U18)- Bank 2



Scroll Title
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titleI2C address for EEPROM

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PinsI2C AddressDesignatorNotes
I2C_SCL, I2C_SDA0x53U64


DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEI0006 SoM has two 1 Gb volatile DDR3 SDRAM IC provided by Integrated Silicon Solution Inc for storing user application code and data.

  • Part number: IS43TR16512BL
  • Supply voltage: 1.35V
  • Speed: 800MHz
  • Temperature: 0 ° C to 95 ° C

Ethernet PHY

Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Intel Cyclone 10 GX SoC connections

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Signal NameConnected toB2BSignal Description

PHY1_MDI0_P

PHY1_MDI0_N

-

-

J2-93

J2-91


PHY1_MDI1_P

PHY1_MDI1_N

-

-

J2-87

J2-85


PHY1_MDI2_P

PHY1_MDI2_N

-

-

J2-81

J2-79


PHY1_MDI3_P

PHY1_MDI3_N

-

-

J2-75

J2-73


ETH1_RSTBank 2A-Connected to DVDDH Voltage
ETH1_MDCBank 2A-Connected to DVDDH Voltage
ETH1_MDIOBank 2A-Connected to DVDDH Voltage
ETH1_TXD0...7Bank 2A-8bit Transfer
ETH1_RXD0...7Bank 2A-8bit Recieve
ETH1_GTXCKBank 2A-
ETH1_TXCLKBank 2A-
ETH1_TXENBank 2A-
ETH1_TXERBank 2A-
ETH1_RXCKBank 2A-Connected to GNG
ETH1_RXDVBank 2A-Connected to GNG
PHY1_INT--Connected to DVDDH Voltage
PHY1_LED1-

J2-69

Connected to DVDDH Voltage
PHY1_LED2-J2-67Connected to GNG
ETH1_CRSBank 2A-
ETH1_XTAL_INETH_CLKIN-From U21 (25MHz MEMS Oschillator)


Intel MAX 10

The TEI0006 is equipped with an Intel MAX 10 device which is a single-chip, non-volatile low-cost programmable logic device (PLD) to integrate the optimal set of system components. Intel MAX 10 (U18) is power and configuration controller on TEI0006 SoM. 

Scroll Title
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titleIntel MAX 10 banks information

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Intel Max 10 BankSignalsConnected to DescriptionNotes
Bank 1AAIN0...7B2B- J2

Bank 1BTCK, TDO, TMS, TDI, JTAGENB2B- J2

Bank 2

PHY1_LED1

PHY1_LED2

Ethernet PHY, U23

Ethernet PHY, U23

Ethernet LED

Ethernet LED

Tight to GND

Tight to DVDDH

F_TCK, F_TDO, F_TDI, F_TMSIntel Cyclone 10 GX (U23) - Bank CSSIntel Cyclone 10 JTAG signals
I2C_SDA, I2C_SCL

EEPROM, U64

B2B, J3 

Programmable Oscillator,U14

I2C EEPROM signals
PLL_RST

Programmable Oscillator, U14

Oscillator reset signal
Bank 3nSTATUS, nCONFIG, CONF_DONEIntel Cyclone 10 GX (U23) - Bank CSSIntel Cyclone 10 Configuration signals
DCLK

Intel Cyclone 10 GX (U23) - Bank CSS

SPI Flash, U1

Intel Cyclone 10

Configuration clock from Flash memory


MSEL0...1Intel Cyclone 10 GX (U23) - Bank CSS

Intel Cyclone 10

Configuration mode signals


DEV_CLRN, INIT_DONEIntel Cyclone 10 GX (U23)- Bank 2A

M10_IO0...4Intel Cyclone 10 GX (U23) - Bank 2A

Bank 5

DIS_GROUP1...4N- Channel MOSFET, T1...4Fast Discharching
MAX_IO23...26B2B, J2Intel MAX 10 GPIO

PG_0.95V, EN_0.95V

PG_1.8VIO, EN_1.8VIO

Voltage Regulator, U7

Voltage Regulator, U7

Power control signals
Bank 6




M10_CLK25MHz Oscillator, U2Intel MAX 10 Clock

VADJ_VS0...2, VADJ_EN

PG_1.35V, EN_1.35V

PG_1.8V, EN_1.8V

PG_VTT, EN_VTT

PG_0V9, EN_0V9

Voltage Regulator, U11

Voltage Regulator, U8

Voltage Regulator, U5

Voltage Regulator, U9

Voltage Regulator, U4

Power control signals
PHY1_33LED1...2

B2B, J2

Ethernet LED

LED_FP_1

LED_FP_2...4

D1

D2...4

User LEDs

Red LED

Green LED

Bank 8

M10_nSTATUS, M10_nCONFIG, M10_CONF_DONE

B2B, J2Intel MAX 10 configuration signals
MAX_IO1...22B2B, J2Intel MAX 10 GPIO


LEDs

Scroll Title
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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D1RedLED_FP_1Active high
D2GreenLED_FP_2Active high
D3GreenLED_FP_3Active high
D4GreenLED_FP_4Active high


Clock Sources

The TEI0006 has three MEMS oscillator and a programmable clock generator. 

Scroll Title
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titleOsillators

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DesignatorDescriptionFrequencyNote
U21MEMS Oscillator25MHz
U15MEMS Oscillator25MHz
U17MEMS Oscillator48MHz
U14Programmable OscillatorVariable



Scroll Title
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titleProgrammable Oscillator connections

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SignalsClock TypeIn/ OutConnected toFrequencyNote

IN1_P

IN1_N

Differential

In

In

Oscillator, U15

GND

25 MHz
IN1..3 DifferentialInB2B, J3Variable

XA

XB

Differential

Oscillator, U17

GND

48 MHz

CLK0...4

DifferentialOutB2B, J325MHz
REFCLK_EMIFPDifferentialOut-Variable
CLK6...7DifferentialOutIntel Cyclon 10 GX (U23)- Bank 1DVariable
CLK8...9DifferentialOutIntel Cyclon 10 GX (U23)- Bank 1CVariable


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 1 A for system startup is recommended.

Power Consumption

Scroll Title
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titlePower Consumption

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FPGATypical Current
Intel Cyclone 10 GXTBD*
Intel MAX 10TBD*


* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Distribution


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Power-On Sequence

Voltage regulators can be enabled through U18(Intel MAX 10)- Bank 6.

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titlePower Sequence


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Power Rails

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titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

Voltage LevelDirectionNotes
VCCIO2K53, 54--1.8 VInput
VADJ140,142--3.0 VOutput
VCCIO2J-29,30
1.8 VInput

3.3V

-149,150-3.3 VOutput
1.8_VIO--1391.8 VOutput


Bank Voltages

Scroll Title
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titleSoC bank voltages.

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FPGAFPGA BankVoltage LevelNotes
Intel Cyclone 10 GXBank 1C0.95 V

Bank 1D

0.95 V
Bank 2A1.8 V
Bank 2J1.8 VVCCIO2J
Bank 2K1.8 VVCCIO2K
Bank 2L3.0 V
Bank 3A1.35 VVDD_DDR
Bank 3B1.35 VVDD_DDR
Intel Max 10Bank 1A3.3 V
Bank 1B3.3 V
Bank 21.8 V1.8VIO
Bank 31.8 V1.8VIO
Bank 53.3V
Bank 63.3V
Bank 83.3V



Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors


TEI0006 module has three Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.

  • 3x REF-192552-02 (160-pins, 80 pins per row) 
  • ST5 Mates with SS5

Operating Temperature: -55°C ~ 125°C
Current Rating: 1.6 A per ContactNumber of Positions: ??

Include Page
PD:4 x 6 SoM SS5/ST5 B2B Connectors
PD:4 x 6 SoM SS5/ST5 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Scroll Title
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titleAbsolute maximum ratings

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SymbolsDescriptionMinMaxUnitNote
VCCCore voltage power supply-0.51.21VIntel Cyclone 10 GX
VCCPPeriphery circuitry and transceiver fabric interface power supply-0.51.21VIntel Cyclone 10 GX
VCCERAMEmbedded memory power supply-0.51.36VIntel Cyclone 10 GX
VCCPTPower supply for programmable power technology and I/O pre-driver-0.52.46VIntel Cyclone 10 GX
VCCIOI/O buffers power supply-0.54.10V

3 V I/O

Intel Cyclone 10 GX

VCCA_PLLPhase-locked loop (PLL) analog power supply-0.52.46VIntel Cyclone 10 GX
VCCH_GXBTransceiver output buffer power supply-0.52.46VIntel Cyclone 10 GX
VCC_ONESupply voltage for core and periphery through on voltageregulator -0.53.9VIntel MAX 10
VCCASupply voltage for phase-locked loop (PLL) regulator and ADC-0.53.9VIntel MAX 10
VCCIOSupply voltage for input and output buffers-0.53.9VIntel MAX 10
T_STGStorage temperature-55125°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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ParameterMinMaxUnitsReference Document
VCC0.870.93VSee Intel Cyclone 10 GX datasheet.
VCCP0.870.93VSee Intel Cyclone 10 GX datasheet.
VCCERAM0.870.93VSee Intel Cyclone 10 GX datasheet.
VCCPT1.711.89VSee Intel Cyclone 10 GX datasheet.
VCCPGM1.711.89VSee Intel Cyclone 10 GX datasheet.
VCCIO2.853.15VSee Intel Cyclone 10 GX datasheet.
VCCA_PLL1.711.89VSee Intel Cyclone 10 GX datasheet.
VCCH_GXB1.711.89VSee Intel MAX 10 datasheet.
VCC_ONE3.1353.465VSee Intel MAX 10 datasheet.
VCCA3.1353.465VSee Intel MAX 10 datasheet.
VCCIO3.135 / 1.713.465 / 1.89VSee Intel MAX 10 datasheet.
T_OP085°CSee Intel MAX 10 datasheet.


Physical Dimensions

  • Module size: 60 mm × 80 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

  • PCB thickness: 1.6 mm
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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



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Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

if not available, set.


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Trenz shop TEI0006 overview page
English pageGerman page


Revision History

Hardware Revision History

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DateRevisionChangesDocumentation Link
2018-08-1001-REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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Document Change History

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


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Disclaimer

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