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- Intel® Cyclone 10 GX Industrial [10CX220YF780I5G]
- Package: FBGA-780
- Speed Grade: 5 (Fastest)
- Temperature: -40°C to 100°C
- Package compatible device 10CX150 and 10CX105 as assembly variant on request possible
- 2x SDRAM DDR3L Memory IC 8 Gbit (1 GByte), 800MHz
- 2x SPI Flash, 1 Gbit (128 MByte)
- 1x Transceiver Full Ethernet 64-QFN
- Programmable Oscillator
- Intel® MAX 10 as System Controller (CPLD)
- 2Kbit 2 Kbit EEPROM Memory
4x User LED
- I/O interfaces:
- 284 266 GPIO
- 118 108 LVDS
- 12 XCVR
Board to Board (B2B):
- Plug-on module with 3 x 160-pin Samtec Razor Beam (ST5) connectors
5 V Power Supply
Dimension: 80m x 60m
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- Intel® MAX 10, U18
- DC/DC convertor, U4...11
- SDRAM DDR3 Memory, U12 ...13- U13
- User LEDs, D1...4
- Ethernet Transceiver, U2
- SPI Flash Memory, U1 - U3
- Intel® Cyclone 10 GX, U23
- EEPROM, U64
- Buffer, U16
- Clock, U14
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| | EEPROM | Programmed | Programmable Oscillator configurationConfiguration | | DDR3 SDRAM | Not Programmed |
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Configuration Signals
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| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE Signal State | MSEL2 | MSEL1 | MSEL0 | Boot Mode |
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MSEL[2:0] | 0 | 1 | 0 | AS / Fast | | 0 | 1 | 1 | AS / Standard | | 0 | 0 | 0 | PS and FPP / Fast | | 0 | 0 | 1 | PS and FPP / Standard |
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By tying the CONF_DONE, nSTATUSNSTATUS, and nCONFIG NCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pinNSTATUS pin, it resets the chain by pulling its nSTATUS NSTATUS pin low.
| Scroll Title |
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| anchor | Table_OV_BP_CS |
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| title | Configuration signals. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signals | Connected to | Description | Note |
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| NCONFIG | 1.8V | Configuration trigger | From U18 ( Intel MAX 10Intel MAX 10) - Bank 3 | | CONF_DONE | 1.8V | Configuration done | To U18 ( Intel MAX 10Intel MAX 10) - Bank 3 | | NSTATUS | 1.8V | Configuration status | To U18 ( Intel MAX 10Intel MAX 10) - Bank 3 | | DCLK | U1 | Configuration clock | To U1 (Flash Memory) From U18 ( Intel MAX 10Intel MAX 10) - Bank 3 | | AS_DATA0...3 | U1 | Configuration data | From U1 (Flash Memory) |
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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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Intel Cyclone 10 GX | Bank 1C | J3 | 24 Single ended (12 Diff pair) | 0.95V | GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P | Bank 1D | J3 | 24 Single ended (12 Diff pair) | 0.95V | GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P | Bank 2A | J2 | 2 Single ended | 1.8V | PERST, CLKUSR | Bank 2J | J2 | 46 Single ended (23 Diff pair) | VCCIO2J |
| Bank 2K | J1 | 46 Single ended (23 Diff pair) | VCCIO2K |
| Bank 2L | J1 | 46 48 Single ended (23 24 Diff pair) | VADJ up to 3 V |
| Bank 3A | - | - | 1.35V | VDD_DDR | Bank 3B | - | - | 1.35V | VDD_DDR | Intel Max 10 | Bank 1A | J2 | 8 Single ended | 3.3V |
| Bank 1B | J2 | 5 Single ended | 3.3V |
| Bank 2 | J3 | 2 Single ended | 1.8VIO |
| Bank 3 | - | - | 1.8VIO |
| Bank 5 | J2 | 4 Single ended | 3.3V |
| Bank 6 | J2 | 2 Single ended | 3.3V |
| Bank 8 | J2 | 24 Single ended | 3.3V |
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| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Intel Cyclone 10 GX SoC connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signal Name | Connected to | B2B | Signal Description |
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PHY1_MDI0_P PHY1_MDI0_N | - - | J2-93 J2-91 |
| PHY1_MDI1_P PHY1_MDI1_N | - - | J2-87 J2-85 |
| PHY1_MDI2_P PHY1_MDI2_N | - - | J2-81 J2-79 |
| PHY1_MDI3_P PHY1_MDI3_N | - - | J2-75 J2-73 |
| | ETH1_RST | U23, Bank 2A | - | Pulled-up to DVDDH Voltage. | | ETH1_MDC | U23, Bank 2A | - | Pulled-up to DVDDH Voltage. | | ETH1_MDIO | U23, Bank 2A | - | Pulled-up to DVDDH Voltage. | | ETH1_TXD0...7 | U23, Bank 2A | - | 8 bit Transfer | | ETH1_RXD0...7 | U23, Bank 2A | - | 8 bit Receive | | ETH1_GTXCK | U23, Bank 2A | - |
| | ETH1_TXCLK | U23, Bank 2A | - |
| | ETH1_TXEN | U23, Bank 2A | - |
| | ETH1_TXER | U23, Bank 2A | - |
| | ETH1_RXCK | U23, Bank 2A | - | Pulled-down to GND. | | ETH1_RXDV | U23, Bank 2A | - | Pulled-down to GND. | | PHY1_INT | - | - | Pulled-up to DVDDH Voltage. | | PHY1_LED1 | U18, Bank 2 | - | Pulled-up to DVDDH Voltage. | | PHY1_LED2 | U18, Bank 2 | - | Pulled-down to GND. | | ETH1_CRS | U23, Bank 2A | - |
| | ETH1_XTAL_IN | ETH_CLKIN | - | From U21 (25MHz MEMS OschillatorOscillator) |
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Intel MAX 10
The TEI0006 is equipped with an Intel MAX 10 device which is a single-chip, non-volatile low-cost programmable logic device (PLD) to integrate the optimal set of system components. Intel MAX 10 (U18) is power and configuration controller on TEI0006 SoM.
| Scroll Title |
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| anchor | Table_SIP_MAX10 |
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| title | Intel MAX 10 banks information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Intel Max 10 Bank | Signals | Connected to | Description | Notes |
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| Bank 1A | AIN0...7 | B2B- J2 |
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| | Bank 1B | TCK, TDO, TMS, TDI, JTAGEN | B2B- J2 |
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| | Bank 2 | PHY1_LED1 PHY1_LED2 | Ethernet PHY, U2 Ethernet PHY, U2 | Ethernet LED Ethernet LED | Pulled-up to DVDDH. Pulled-down to GND. | | F_TCK, F_TDO, F_TDI, F_TMS | Intel Cyclone 10 GX (U23) - Bank CSS | Intel Cyclone 10 JTAG signals |
| | I2C_SDA, I2C_SCL | EEPROM, U64 B2B, J3 Programmable Oscillator, U14 | I2C EEPROM signals |
| | PLL_RST | Programmable Oscillator, U14 | Oscillator reset signal |
| | Bank 3 | NSTATUS, NCONFIG, CONF_DONE | Intel Cyclone 10 GX (U23) - Bank CSS | Intel Cyclone 10 Configuration signals |
| | DCLK | Intel Cyclone 10 GX (U23) - Bank CSS SPI Flash, U1 | Intel Cyclone 10 Configuration clock from Flash memory |
| | MSEL0...1 | Intel Cyclone 10 GX (U23) - Bank CSS | Intel Cyclone 10 Configuration mode signals |
| | DEV_CLRN, INIT_DONE | Intel Cyclone 10 GX (U23) - Bank 2A |
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| | M10_IO0...4 | Intel Cyclone 10 GX (U23) - Bank 2A |
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| Bank 5
| DIS_GROUP1...4 | N- Channel MOSFET, T1...4 | Fast Discharching |
| | MAX_IO23...26 | B2B, J2 | Intel MAX 10 GPIO |
| PG_0.95V, EN_0.95V PG_1.8VIO, EN_1.8VIO | Voltage Regulator, U7 Voltage Regulator, U6 | Power control signals |
| Bank 6
| M10_CLK | 25MHz 25 MHz Oscillator, U21 | Intel MAX 10 Clock |
| VADJ_VS0...2, VADJ_EN PG_1.35V, EN_1.35V PG_1.8V, EN_1.8V PG_VTT, EN_VTT PG_0V9, EN_0V9 | Voltage Regulator, U11 Voltage Regulator, U8 Voltage Regulator, U5 Voltage Regulator, U9 Voltage Regulator, U4 | Power control signals |
| | PHY1_33LED1...2 | B2B, J2 | Ethernet LED |
| LED_FP_1 LED_FP_2...4 | D1 D2...4 | User LEDs | Red LED Green LED | | Bank 8 | M10_nSTATUS, M10_nCONFIG | B2B, J2 | Intel MAX 10 configuration signals |
| | MAX_IO1...20, 22 | B2B, J2 | Intel MAX 10 GPIO |
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| Scroll Title |
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| anchor | Table_OBP_CLK_PO |
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| title | Programmable Oscillator connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signals | Clock Type | In/ Out | Connected to | Frequency | Note |
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IN0_P IN0_N | Differential | In In | Oscillator, U15 GND | 25 MHz |
| | IN1..3 | Differential | In | B2B, J3 | Variable |
| XA XB | Differential |
| Oscillator, U17 GND | 48 MHz |
| CLK0 | Differential | Out | Intel Cyclon 10 GX (U23)- Bank 2A | 25MHz25 MHz |
| CLK1...4 | Differential | Out | B2B, J3 | 25MHz25 MHz |
| | REFCLK_EMIFP | Differential | Out | Intel Cyclon 10 GX (U23)- Bank 3B | Variable |
| | CLK6...7 | Differential | Out | Intel Cyclon 10 GX (U23)- Bank 1D | Variable |
| | CLK8...9 | Differential | Out | Intel Cyclon 10 GX (U23)- Bank 1C | Variable |
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| Scroll Title |
|---|
| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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| Power Rail Name | B2B Connector J1 Pin | B2B Connector J2 Pin | B2B Connector J3 Pin | Voltage Level | Direction | Notes |
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| VIN | 145, 147,149, 151, 153, 155, 157, 159 | - | - | 5 V | Input |
| | VCCIO2K | 53, 54 | - | - | 1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V or 3.0 V | Input |
| | VADJ | 140,142 | - | - | adjustable between 1.8 V - 3.0 V | Output | Voltages according to EP53A8HQI datasheet | | VCCIO2J | - | 29,30 | - | 1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V or 3.0 V | Input |
| 3.3V | - | 149,150 | - | 3.3 V | Output |
| | 1.8_VIO | - | - | 139 | 1.8 V | Output |
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | SoC bank voltages. |
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| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| FPGA | FPGA Bank | Voltage Level | Notes |
|---|
| Intel Cyclone 10 GX | Bank 1C | 0.95 V |
| Bank 1D | 0.95 V |
| | Bank 2A | 1.8 V | 1.8VIO | | Bank 2J | 1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V or 3.0 V | VCCIO2J | | Bank 2K | 1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V or 3.0 V | VCCIO2K | | Bank 2L | adjustable between 1.8 V - 3.0 V | Voltages according to EP53A8HQI datasheet | | Bank 3A | 1.35 V | VDD_DDR | | Bank 3B | 1.35 V | VDD_DDR | | Intel Max 10 | Bank 1A | 3.3 V |
| | Bank 1B | 3.3 V |
| | Bank 2 | 1.8 V | 1.8VIO | | Bank 3 | 1.8 V | 1.8VIO | | Bank 5 | 3.3V |
| | Bank 6 | 3.3V |
| | Bank 8 | 3.3V |
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Board to Board Connectors
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