Scroll Title

anchor	Table_OV_RST
title	Reset process.

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

Signal

B2BNote

RESIN

JBC3-130Board Reset

Signals, Interfaces and Pins

130 Board Reset

Signals, Interfaces and Pins

Page properties
hidden true id Comments
Notes : For carrier or stand-alone boards use subsection
Page properties
hidden true id Comments
Notes : For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example: SD USB ETH FMC ... For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example JTAG UART I2C MGT ...

...

Scroll Title
anchor Table_SIP_B2B title General PL I/O to B2B connectors information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true B2B Connector Interface Number of I/O Notes JBC1 RJ45, J1B-J1C 1 Differential pair, 2 Single Ended Yellow, Green LEDs RJ45, J1A 4 Differential pair, 8 Single Ended RJ45, J2B-J2C 1 Differential pair, 2 Single Ended Yellow, Green LEDs RJ45, J2A 4 Differential pair, 8 Single Ended TE0790 Base, J8 4 Single Ended TE0790 Base, J7 1 Single Ended USB A Stacked, U7 2 Single Ended Power Switch, U1 2 Single Ended SMD Line Filter, L6 1 Differential pair, 2 Single Ended SMD Line Filter, L7 1 Differential pair, 2 Single Ended JBC2 Module TE0782...4 FPGA, Bank 111-112 16 Differential pair, 32 Single Ended MGT_RX8...15, MGT_TX8...15 Module TE0782...4 FPGA, Bank 34 1 Differential pair, 2 Single Ended J1_B34_VRP, J1_B34_VRN Module TE0782...4 FPGA, Bank 34 1 Differential pair, 2 Single Ended J1_B33_VRP, J1_B33_VRN JBC3 TE0790 Base, J8 4 Single Ended M_TCK, M_TMS, M_TDO, M_TDI TE0790 Base, J7 4 Single Ended 2 Single Ended 1 Single Ended TCK, TMS, TDO, TDI UART RX/TX RESIN DIP Switch, S1-A 1 Single Ended JTAGENB Module SMA Coaxial, J3...6 2 Differential pair, 4 Single Ended MGT_RX0, MGT_TX0 Module TE0782...4 FPGA, Bank 109-110 16 Differential pair, 32 Single Ended MGT_ RX0 RX1...7, MGT_TX0...7

JTAG Interface

Two JTAG access accesses to the TE0782...4 SoMs TEBT0782 SoMs are available through B2B connector JMXJB3. JTAGENB is connected to DIP Switch S1-A.

Scroll Title
anchor Table_SIP_JTG title JTAG pins connection
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true TE0790 Base JTAG Signal B2B Connector Notes J8 TMS JB3C-142 TDI JB3C-147 TDO	TCK	JTAG_EN

MIO Pins

...

hidden	true
id	Comments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

JB3C-148 TCK JB3C-141 J8 M_TMS JB3B-182 M_TDI JB3B-187 M_TDO JB3B-188 M_TCK JB3B-181

UART

Scroll Title
anchor Table_SIP_UART title UART Pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal State B2B Notes XMOD_A JB3C- 129 Used as UART TX line XMOD_B JB3C- 135 Used as UART RX line

RJ45 Connectors

...

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

...

Scroll Title
anchor Table_OBPSIP_MIOsRJ45 title MIOs pinsRJ45s Connections to B2B Connectors
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal Name RJ45-J1 RJ45-J2 MIO Pin Connected to Notes B2B	Notes

...

PHY_MDI0_P JB1A-23 JB1A-39 PHY_MDI0_N JB1A-21 JB1A-37 PHY_MDI1_P JB1A-19 JB1A-35 PHY_MDI1_N JB1A-17 JB1A-33 PHY_MDI2_P JB1A-15 JB1A-31 PHY_MDI2_N JB1A-13 JB1A-29 PHY_MDI3_P JB1A-11 JB1A-27 PHY_MDI3_N JB1A-9 JB1A-25 J2_TX9_P JB1A-95 - LED Green/Yellow J2_TX9_N JB1A-97 - LED Green/Yellow J2_RX9_N - JB1A-96 LED Green/Yellow J2_RX9_P - JB1A-98 LED Green/Yellow

USB A Stacked

The USB A Stacked, U7 is a dual port USB Socket which provides two USB connectors.

Scroll Title
anchor Table_SIP_USB title Dual Port USB Connections
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style

Page properties
hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

Page properties
hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Designator

Scroll Title
anchor Table_OBP title On board peripherals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal Name Port A Port B	Chip/Interface

		Notes