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anchorTable_SIP_CPLD
titleSC CPLD pin mapping

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Signal nameSC CPLD PinConnected toFunctionNotes
ACBUS0A4FTDI U4, pin 22GPIO's available to user











(FIFO or other FTDI functions when FTDI reprogrammed)











ACBUS1B4FTDI U4, pin 23
ACBUS2A5FTDI U4, pin 24
ACBUS3B5FTDI U4, pin 25
ACBUS4A6FTDI U4, pin 26
ACBUS5B6FTDI U4, pin 27
ACBUS6A7FTDI U4, pin 28
ACBUS7A8FTDI U4, pin 29
ADBUS4A2FTDI U4, pin 17
ADBUS5B2FTDI U4, pin 18
ADBUS6A3FTDI U4, pin 19
ADBUS7B3FTDI U4, pin 20
TCKG2FTDI U4, pin 12Forwarded JTAG signals from FTDI chip.



(FIFO or other FTDI functions when FTDI reprogrammed)



TDIF5FTDI U4, pin 13
TDOF6FTDI U4, pin 14
TMSG1FTDI U4, pin 15
M_TCKH5JB2, pin 1004x5 Module JTAG



Bank with VCCIO is VREF_JTAG from Module



M_TDIJ2JB2, pin 96
M_TDOJ1JB2, pin 98
M_TMSH6JB2, pin 94
FMC_TCKF8J1, pin D29FMC JTAG




TRST not used



FMC_TDIM7J1, pin D30
FMC_TDON7J1, pin D31
FMC_TMSM8J1, pin D33
FMC_TRSTN8J1, pin D34
PCIE_TCKL11J3, pin A5PCIe JTAG




Currently not used




PCIE_TDIN12J3, pin A6
PCIE_TDOM12J3, pin A7
PCIE_TMSM13J3, pin A8
PCIE_TRSTG10J3, pin B9
PCIE_PERSTF12J3, pin A11Indication that PCIe Bus is up (power, clocks)
EN_FMCL4U14, pin 9Enable switched 3.3V FMC powerpulled down
EN_FMC_VADJK7U1, pin 41Enable IO power FMC_VADJpulled down
EN_PERF13Q4, pin 5Enable perepherie power 3V3_PERpulled down
FAN_FMC_ENK8Q1, pin 5Enable FMC FAN
FMC_PG_C2MM5J1, pin D1Indicate that all FMC related powers are uppulled up
FMC_PRSNT_M2C_LE9J1, pin H2Indicate if FMC installedLow when FMC present
FMC_SCLJ8J1, pin C31I2C 2-wire serial busMUX in CPLD
FMC_SDAF9J1, pin C30
PG_FMC_VADJJ6U1, pin 35Indicate FMC VADJ power is up
FF_RSTLB9J13, pin 6  and J18, pin 6Reset configurationBoth FF are resetted simultanously when pulled LOW
FFA_INTLE8J13, pin 5Indicate interrrupt

LOW when fault condition, pulled up

FFA_MPRSC10J13, pin 3Indicate FF Module installedLOW when Module present, pulled up
FFA_MSELC9J13, pin 4Select attached FF ModulePull low to use I2C
FFA_SCLD6J13, pin 8I2C 2-wire serial busMUX in CPLD
FFA_SDAE6J13, pin 7
FFB_INTLA10J18, pin 5Indicate interrruptLOW when fault condition, pulled up
FFB_MPRSA11J18, pin 3Indicate FF Module installedLOW when Module present, pulled up
FFB_MSELB10J18, pin 4Select attached FF ModulePull low to use I2C
FFB_SCLD8J18, pin 8I2C 2-wire serial busMUX in CPLD
FFB_SDAA9J18, pin 7
CPLD_IO_1B12JB1, pin 88(M)IOs from 4x5 Module(M)IOs used for ETH PHY LEDs

CPLD_IO_2A12JB1, pin 92(M)IOs from 4x5 Module
M10_RSTD1

TP22




Not used


M10_RXE4TP24
M10_TXE3TP23
EN1D11JB1, pin 27Enable on module powerDepends on module, on some similar to reset.
MODEB11JB1, pin 31Boot Mode selectionFor Zynq modules only. (LOW → SD, HIGH → primary QSPI)
NOSEQE13JB1, pin 8Disable module CPLD power managementDepends on module. On some modules no extended CPLD power management avaialble.
PGOODC11JB1, pin 29Power good signal

This is only for monitoring, do not use as powerenable! Pulled up.

RESINE12JB2, pin 17Module ResetAktive LOW
M3.3VOUTM4JB2, pin 9 and 11Indicates module power is upUsed for perepherie power enable.
SFPA_LOSM10J12, pin 8SFP signal lossHIGH indicates signal loss
SFPA_M-DEF0F10J12, pin 6SFP modul absentHIGH when module physically absent
SFPA_RS0N10J12, pin 7SFP rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_RS1M11J12, pin 9SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_SCLL10J12, pin 5I2C 2-wire serial busMUX in CPLD
SFPA_SDAN9J12, pin 4
SFPA_TX_DISM9J12, pin 3SFP transmitter disableHIGH disables transmitter
SFPA_TX_FAULTG9J12, pin 2Indicates SFP laser faultHIGH indicates fault
VID0_FMC_VADJE10U1, pin 34FMC_VADJ Voltage selectChip internal pulled up


VID1_FMC_VADJJ7U1, pin 33
VID2_FMC_VADJL5U1, pin 32
VID0K6S2-1For FMC_VADJ Voltage select





VID1N5S2-2
VID2N4S2-3
JTAGENE5S2-4

FMC_JTAGL3S2-6

CM0M3S2-7

CM1L2S2-8

CM2K2S3-1

USR0K1S3-2

USB_OCD9U12, pin 5

BUTTONN6S1

LED1J5D1user LED
LED2K5D2
-C2D4Status LEDFor further explanation see SC CPLD Firmware description
PHY_LED1D12J9Phy LEDs







PHY_LED1RC13J9
PHY_LED2B13J9
PHY_LED2RC12J9
A_00_NJ10JB1, pin 38Module to CPLD communication














Currently "three wire" I2C  and RGPIO, see SC CPLD Firmware description













A_00_PK10JB1, pin 36
A_01_NL12JB1, pin 35
A_01_PK11JB1, pin 37
A_02_NJ12JB1, pin 41
A_02_PK12JB1, pin 39
A_03_NH10JB1, pin 44
A_03_PJ9JB1, pin 42
A_04_NH13JB1, pin 47
A_04_PJ13JB1, pin 45
A_05_NH8JB1, pin 57
A_05_PH9JB1, pin 55
A_06_NG12JB1, pin 49
A_06_PG13JB1, pin 51
A_07L13JB1, pin 34


FTDI FT2232H

SDIO Port Expander

Configuration DIP-switches

Jumper

Push Button

On-board LEDs

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

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anchorFigure_PWR_PD
titlePower Distribution
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The TEF1002 board has an on-board microUSB 2.0 (J10) high-speed to JTAG/UART/FIFO IC FT2232H (U4) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed to the B2B connector. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Refer to the FTDI datasheet to get information about other options of the FT2232H chip.

Scroll Title
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titleFT2232H interface connections

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FTDI U4 pinSignal Schematic NameConnected to,  PinFunctionNotes
Pin 22ACBUS0SC CPLD U4, A4GPIO's available to user











(FIFO or other FTDI functions when FTDI reprogrammed)











Pin 23ACBUS1SC CPLD U4, B4
Pin 24ACBUS2SC CPLD U4, A5
Pin 25ACBUS3SC CPLD U4, B5
Pin 26ACBUS4SC CPLD U4, A6
Pin 27ACBUS5SC CPLD U4, B6
Pin 28ACBUS6SC CPLD U4, A7
Pin 29ACBUS7SC CPLD U4, A8
Pin 17ADBUS4SC CPLD U4, A2
Pin 18ADBUS5SC CPLD U4, B2
Pin 19ADBUS6SC CPLD U4, A3
Pin 20ADBUS7SC CPLD U4, B3
Pin 12TCKSC CPLD U4, G2JTAG signals forward to SC CPLD U4

(FIFO or other FTDI functions when FTDI reprogrammed)

Pin 13TDISC CPLD U4, F5
Pin 14TDOSC CPLD U4, F6
Pin 15TMSSC CPLD U4, G1
Pin 32BDBUS0JB1, 91UART
Pin 33BDBUS1JB1, 86


SDIO Port Expander

The TEF1002 is equipped with the Texas Instruments TXS02612 SDIO Port Expander (U3), which is used as a SDIO level shifter. Port A is connected to the  B2B connector J1. The IO Voltage VCCA_SD of this port is selected by jumper J7 and has to be set according to the module  attached. Port B0 is directly connected to the microSD Card connector (J8).

Scroll Title
anchorTable_OBP_SDIO
titleSDIO Port Expander connections

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Port Expander U3 pinSignal Schematic NameConnected to B2B  PinNotes
Pin 6SD-D0JB1, Pin 24Signals levelshiftet to 3.3V and connected to Card holder (J8)
Pin 7SD-D1JB1, Pin 22
Pin 1SD-D2JB1, Pin 20
Pin 3SD-D3JB1, Pin 18
Pin 4SD-CMDJB1, Pin 26
Pin 9SD-CCLKJB1, Pin 28


Configuration DIP-switches

S2 and S3 provide 10 dip-switchs for configuration purpurses. Some of them are hard wired others are SC CPLD firmware dependent. If Firmware dependet, the functions in Notes are for the actual delivery firmware. For further descriptions see firmware description.

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titleDIP-switches

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SwitchSignal Schematic NameConnected to,  PinNotes
S2-1VID0SC CPLD U11, K6SC CPLD firmware dependent, used for FMC_VADJ, see table below.
S2-2VID1SC CPLD U11, N5
S2-3VID2SC CPLD U11, N4
S2-4JTAGENSC CPLD U11, E5OFF TEF1002 SC CPLD JTAG; ON module/FMC JTAG, hard wired.
S2-5M_JTAGENJB1, Pin 90When S2-4 ON and S2-6 OFF: OFF 4x5 module CPLD JTAG, ON 4x5 module FPGA/SOC JTAG, hard wired.
S2-6FMC_JTAGSC CPLD U11, L3SC CPLD firmware dependent. When S2-4 ON: ON FMC JTAG; OFF 4x5 module JTAG
S2-7

CM0

SC CPLD U11, M3SC CPLD firmware dependent, EN1
S2-8CM1SC CPLD U11, L2SC CPLD firmware dependent, NOSEQ
S3-1CM2SC CPLD U11, K2SC CPLD firmware dependent, BOOT MODE
S3-2USR0SC CPLD U11, K1SC CPLD firmware dependent, Override FMC_EN_VADJ



Scroll Title
anchorTable_OBP_FMC_VADJ
titleFMC_VADJ selection

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S2-1S2-2S2-3Output Voltage
OFFOFFOFF3.3V
OFFOFFON2.5V
OFFONOFF1.8V
OFFONON1.5V
ONOFFOFF1.25V
ONOFFON1.2V
ONONOFF0.8V


Jumper

There are two voltage select jumpers available. J4 is used to select the SDIO signal voltage and J7 is used to select VCCIOA IO Voltage. Both have to be selected according to the attached 4x5 module capabilities (See TRM of your module).

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titleJumper positions

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JumperPower rail3.3V1.8V
J4VCCIOA1-22-3
J7VCCA_SD1-22-3


Push Button

There is on push button (S1) on the TEF1002. It is connected to the SC CPLD (U11 Pin N6). The function is firmware dependet. In the actual delivery firmware it is used as module reset connected to B2B JB2 Pin 17 (RESIN). For further descriptions see firmware description.

Pin Header

Pin 1 of the 2x1 pin header J6 is directly connected to the B2B connetor JB1 PSBATT pin. Pin to is connected to GND. This pin header can be used to supply the

Warning

Check the TRM of the attached 4x5 Module for the correct Battery voltage. Do not short or swap polarity, this may damage the module!

On-board LEDs

There are 4 green LEDs on the board, two of them are for user purpurses and controlabe via the RGPIO of the actual delivery firmware.

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titleLED Overview

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LEDConnected toFunctionNotes
D1SC CPLD U11, Pin J5User LEDsSC CPLD firmware dependet

D2

SC CPLD U11, Pin K5
D33V3INPowerON when 3.3V generated from 12V input is up
D4SC CPLD U11, Pin C2StatusSC CPLD firmware dependet, for further dexcription see firmware description.


Power and Power-On Sequence

Power Consumption

Power consumption depends on the attached  4x5 module and configuration, as well as FPGA design. Generally a power supply with minimum current capability of 3A at 12V for system startup is recommended.

Power Distribution Dependencies

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anchorFigure_PWR_PD
titlePower Distribution


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Power-On Sequence

Power up sequenz is depicted in the following figure. Most of the enables are handled by the SC CPLD and are therefore Firmware dependent. The Power up meets all criteria to power up 4x5 modules.

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titlePower Sequency


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Power Rails


In the following table power rails acceccible for in or output on any connectors are summarized.

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titlePower Rails

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Connector, PinsVoltageDirectionNotes
J15, 1,2,312VINTEF1002 supply voltage
J16, 15VOUTUSB-VBUS_R
J6, 1Depends on 4x5 ModuleINDirectly connected to B2B PSBATT pin
J2, 25VOUTFMC Fan Connector
JB1, 10,121,8V/3.3VOUTVCCIOA, selected by J4
JB1, 14,163.3VOUTModule supply voltage
JB1, 401.8VINModule 1.8V output
JB1, 80Depends on 4x5 ModuleOUTDirectly connected to pinheader J6 PSBATT
JB1, 2,4,65VOUTModule power input
JB2, 1,3,5,75VOUTModule power input
JB2, 9,113.3VINModule 3.3V output
JB2, 2,4,6,8,100,8V ... 3.3VOUTModule VCCIOB, VCCIOC, VCCIOD connected to FMC VADJ
JB2, 20Depends on 4x5 ModuleINModule DDR power output
JB2, 92Depends on 4x5 ModuleINVREF_JTAG
J13, 1,103.3VOUTFFA supply voltages
J18, 1,103.3VOUTFFB supply voltages

Power-On Sequence

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anchorFigure_PWR_PS
titlePower Sequency
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Voltage Monitor Circuit

Power Rails

Bank Voltages

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
    Include Page
    PD:4 x 5 SoM LSHM B2B Connectors
    PD:4 x 5 SoM LSHM B2B Connectors

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titleModule absolute maximum ratings.

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ParameterMinMaxUnitsReference DocumentReference Document

VIN supply voltage

-0.320

V

TPS6217 datasheet

Note: voltage limitations are not valid for connected FMC module

Storage temperature

-40

+100

°C

SML-P11 LED datasheet


Recommended Operating Conditions

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titleRecommended Operating Conditions.

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ParameterMinMaxUnitsReference Document
VIN supply voltage11.412.6V12V nominal, ANSI/VITA 57.1 power specification for FMC connector

Board Operating Temperature Range

085°C

10M08SAU169C8G CPLD datasheet


Physical Dimensions

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titlePhysical dimensions drawing
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Variants Currently In Production

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titleTrenz Electronic Shop Overview

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Trenz shop TE0xxx TEF1002 overview page
English pageGerman page


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Scroll Title
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titleHardware Revision Number
draw.io Diagram
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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titleDocument change history.

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DateRevisionContributorDescription

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  • change listinitial version

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