Template Change history: Date | Version | Changes | Author |
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| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Perihery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
- add table size as macro
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Important General Note:
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Note for Download Link of the Scroll ignore macro: |
Overview
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The Trenz Electronic TEI0022 is a SoC board based on Intel Cyclone V FPGA, an Ethernet PHY, one GByte DDR3 SDRAM per HPS and FPGA and one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.
Refer to http://trenz.org/tei0022-info for the current online version of this manual and other available documentation.
Key Features
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- SoC FPGA
- Intel Cyclone V (5CSEMA5F31C8N)
- Package: FBGA 896 pins
- Speed Grade: 8
- Temperature: Commercial (Tj = 0 °C to 85 °C)
- RAM/Storage
- 1 GByte DDR3 SDRAM for HPS
- 1 GByte DDR3 SDRAM for FPGA
- 32 MByte SPI for HPS
- 32 MByte SPI for FPGA
- On Board
- up to 7 x SMA Connector
- Temperature Sensor
- Intel MAX10 for board management
- Interface
- LPC FMC Connector
- 4 x Pmod Connector
- JTAG
- UART via micro USB B Connector (for FPGA)
- UART via micro USB B Connector (for HPS)
- 4 x USB 2.0 Host
- Ethernet via RJ45 Connector
- SD Card
- HDMI
- Power
- 12 V Input supply voltage
- Dimension
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Block Diagram
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Intel Cyclone V, U10
- DDR3 SDRAM, U26...27
- DDR3 SDRAM, U28...29
- FMC, J4
- Pmod, P1...4
- SD Card Connector, J3
- Ethernet PHY, U1
- RJ45 Connector, J1
- USB PHY, U8
- USB HUB, U33
- USB Connector, J2, J12
- HDMI Transmitter, U23
- HDMI Connector, J11
- Intel MAX10, U41
- Micro USB to UART Interface, J5, U30
- USB to JTAG , U21
- Micro USB JTAG and UART, J13
- SMA Connector
- Push Button, S1, S3...5
- LED
- 4-Bit DIP Switch, S2, S7...8
- 12 V Power Jack, J6
- Clock Generator, U48
- Programmable Clock Generator, U3
- QSPI - FPGA PS, U6
- QSPI - FPGA PL, U15
- Temperature Sensor, U16
- EEPROM, U38
Initial Delivery State
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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title | Initial delivery state of programmable devices on the module |
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Storage device name | Content | Notes |
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HPS SPI Flash (U6) | Not programmed | HPS Configuration | FPGA SPI Flash (U15) | Not programmed | FPGA Configuration | MAC EEPROM (U38) | MAC programmed, otherwise not programmed | Ethernet MAC | FTDI EEPROM (U31) | Programmed | FTDI Functionality | Programmable Clock Generator Si5338 (U3) | Programmed, CLK0 - 50M, CLK1 - 50M, CLK2 - 25M, CLK3 - 50M | -- |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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Boot Mode must be set using DIP Switch S7 on the module TEI0022. Please note that the DIP Switch is active low.
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anchor | Table_OV_BP |
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title | Boot process. |
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MODE Signal State | Boot Mode | Notes |
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S7-1 (BOOTSEL0) | S7-2 (BOOTSEL1) | FPGA | ON | ON | -- | SD Card | ON | OFF | -- | QSPI flash | OFF | OFF | -- |
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title | Reset process. |
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Reset | Button | Notes |
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HPS cold reset | S1 | -- | HPS warm reset | S3 | -- | FPGA reset | S4 | -- |
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Signals, Interfaces and Pins
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FMC LPC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
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anchor | Table_SIP_FMC |
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title | FMC connectors information |
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The FMC connector provides further interfaces like JTAG and I²C:
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anchor | Table_SIP_FMC_Interfaces |
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title | FMC connector pin-outs of available interfaces |
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Interface | I/O Signal Count | Pin schematic Names / FMC Pins | Connected to | Notes |
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JTAG | 5 | FMC_TCK, Pin J4-D29 FMC_TMS, Pin J4-D33 FMC_TDI, Pin J4-D30 FMC_TDO, Pin J4-D31 FMC_TRST#, Pin J4-D34 | Intel MAX10 U41, Bank 3 | VCCIO: +3.3V | I2C | 2 | FMC_SCL, Pin J4-C30 FMC_SDA, Pin J4-C31 | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7A | I2C-lines pulled-up to +3.3V | Control Lines | 2 | FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V) FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V) | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 5B / 7C | 'PG' = 'Power Good'-signal 'C2M' = carrier to (Mezzanine) module 'M2C' = (Mezzanine) module to carrier |
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Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:
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anchor | Table_SIP_FMC_Voltage |
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title | Available VCCIO voltages on FMC connector |
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VCCIO Schematic Name | FMC Connector J4 Pins | Notes |
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+12.0V_FMC | C35/C37 | extern 12 V power supply | +3.3V_FMC | D36/D38/D40/C39 | 3.3 V peripheral supply voltage | +3.3V | D32 | 3.3 V peripheral supply voltage | FMC_VADJ | H40/G39 | adjustable FMC VCCIO voltage, supplied by DC-DC converter U43 | FMC_VREF_A_M2C | H1 | adjustable reference voltage |
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Pmod Connector
The TEI0022 board offers four Pmod (2x6 pins, SMD) connectors which provides as a standard modular interface single ended I/O pins for use with extension modules.
Following table gives an overview of the Pmod connectors and the signals routed to the attached Intel Cyclone V (U10):
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anchor | Table_SIP_PMOD |
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title | Pmod connectors pin description |
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Pmod Connector P1 Pin | Signal Schematic Name | Connected to Intel Cyclone V, U10 | Notes |
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1 | P0_IO1 | Pin AD9 | -- | 2 | P0_IO2 | Pin AD11 | -- | 3 | P0_IO3 | Pin AD12 | -- | 4 | P0_IO4 | Pin AC12 | -- | 7 | P0_IO5 | Pin AC9 | -- | 8 | P0_IO6 | Pin AD10 | -- | 9 | P0_IO7 | Pin AA12 | -- | 10 | P0_IO8 | Pin AB12 | -- | Pmod Connector P2 Pin | Signal Schematic Name | Connected to Intel Cyclone V, U10 | Notes | 1 | P1_IO1 | Pin AG2 | -- | 2 | P1_IO2 | Pin AF4 | -- | 3 | P1_IO3 | Pin AF8 | -- | 4 | P1_IO4 | Pin AD7 | -- | 7 | P1_IO5 | Pin AG1 | -- | 8 | P1_IO6 | Pin AF5 | -- | 9 | P1_IO7 | Pin AE7 | -- | 10 | P1_IO8 | Pin AE9 | -- | Pmod Connector P3 Pin | Signal Schematic Name | Connected to Intel Cyclone V, U10 | Notes | 1 | P2_IO1 | Pin AH5 | -- | 2 | P2_IO2 | Pin AH3 | -- | 3 | P2_IO3 | Pin AJ2 | -- | 4 | P2_IO4 | Pin AG3 | -- | 7 | P2_IO5 | Pin AG5 | -- | 8 | P2_IO6 | Pin AH4 | -- | 9 | P2_IO7 | Pin AH2 | -- | 10 | P2_IO8 | Pin AJ1 | -- | Pmod Connector P4 Pin | Signal Schematic Name | Connected to Intel Cyclone V, U10 | Notes | 1 | P3_IO1 | Pin AE12 | -- | 2 | P3_IO2 | Pin AF9 | -- | 3 | P3_IO3 | Pin AG8 | -- | 4 | P3_IO4 | Pin AG6 | -- | 7 | P3_IO5 | Pin AE11 | -- | 8 | P3_IO6 | Pin AF10 | -- | 9 | P3_IO7 | Pin AG7 | -- | 10 | P3_IO8 | Pin AF6 | -- |
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SMA Connector
The TEI0022 board offers up to seven SMA connectors for trigger and clock input and output.
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anchor | Table_SIP_SMA |
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title | SMA connectors |
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orientation | portrait |
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SMA Connector | Signal Schematic Names | Connected to | Notes |
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J7 | SMA_CLK_OUT_p | Clock Generator U3, Pin 22 | Assembly option | J10 | SMA_CLK_OUT_n | Clock Generator U3, Pin 21 | Assembly option | J8 | TRIGGER_OUTPUT | Intel Cyclone V U10, Pin AE29 | -- | J9 | TRIGGER_INPUT | Intel Cyclone V U10, Pin AA26 | -- | J15 | EXT_CLK_INPUT | Intel Cyclone V U10, Pin Y26 | -- | J17 | CLK_INPUT | Intel Cyclone V U10, Pin AD29 | -- | J18 | SMA_CLK_IN | Clock Generator U3, Pin 1 | Assembly option |
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FAN Connector
The TEI0022 board offers a FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usable.
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anchor | Table_SIP_FAN |
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title | FAN connectors |
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orientation | portrait |
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Connector | Signal Schematic Names | Connected to | Notes |
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2-Pin FAN Connector J16, 5 V or 12 V power supply depending on R270/271 with BTS4141N High Side Switch U55 | FAN_EN, (High Side Switch U55, Pin 3) | Intel MAX10 U41, Pin D13 | Intel Cyclone V cooling FAN |
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Micro USB Connector (JTAG)
According to the JTAGEN and JTAGSEL[1..0] pins the management controller Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.
JTAG access is controlled by the DIP switches S7 and S8 on the module TEI0022. Please note that the DIP Switches are active low.
Scroll Title |
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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orientation | portrait |
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JTAG selection | JTAG Signal State | Note | S7-3 (JTAGSEL0) | S7-4 (JTAGSEL1) | S8-4 (JTAGEN) |
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X | X | ON | Intel MAX10 | -- | ON | ON | OFF | Intel Cyclone V HPS | -- | ON | OFF | OFF | Intel Cyclone V FPGA | -- | OFF | ON | OFF | FMC | -- |
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anchor | Figure_OV_JTAG |
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title | TEI0022 JTAG |
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diagramName | Figure_OC_JTAG |
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diagramWidth | 625 |
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Micro USB Connector (UART)
A UART connection between the USB B connector J5 and the Intel Cyclone HPS U10 is possible via the FT234XD (U30) chip.
USB Connector
On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available (J2, J12).
HDMI Connector
The TEI0022 provides an HDMI Connector J11.
SD Card Connector
SD Card connector J3 is connected to the Intel Cyclone V U10.
RJ45 Connector
The board TEI0022 provides an ethernet interface via the RJ45 connector J1.
I2C
The TEI0022 provides three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is used to connect the HDMI device to the Intel Cyclone V FPGA. The third bus is used to handle the other on-board I2C devices. Via assembly option, it is possible to connect bus two to bus three.
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anchor | Table_OBP_I2C |
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title | On-board peripherals' I2C-interfaces device slave addresses |
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orientation | portrait |
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Bus | I2C Device | Designator | I2C Address | Schematic Names of I2C Bus Lines | Notes |
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HPS I2C | Temperature Sensor | U16 | 0x4A | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | HPS I2C | Programmable Clock Generator | U3 | 0x70 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | HPS I2C | EEPROM | U38 | 0x50 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | HDMI I2C | HDMI | U23 | 0x72 | HDMI_I2C_SCL / _I2C_SDA | 3.3 V reference voltage | HPS FMC I2C | FMC | J4 | 0x50 | FMC_SCL / FMC_SDA | 3.3 V reference voltage |
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title | TEI0022 I2C |
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tbstyle | top |
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diagramWidth | 541 |
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On-board Peripherals
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scroll-pdf | true |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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cellHighlighting | true |
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System Controller Intel MAX 10
The TEI0022 is equipped with an Intel MAX 10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.
Intel Cyclone V
The Intel Cyclone V device used at the TEI0022 board is a SoC with integrated ARM-based HPS. The 5CSEMA5F31C8N version delivers one hard memory controller, 80K logic elements in an FineLineBGA (FBGA) with 896 pins for the commercial temperature range of TJ = 0...85 °C with speed grade eight.
DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA (U26, U27) and HPS (U28, U29) for storing user application code and data.
- Part number: IS43TR16256BL-125KBLI
- Supply voltage: 1.5 V
- Speed: TBD
- Temperature: TC = -40 °C up to 95 °C
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U48).
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to HPS connections |
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orientation | portrait |
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Bank | Signal Name | Signal Description |
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7B | ETH_TXCK | RGMII Transmit Reference Clock | 7B | ETH_TXD0 | RGMII Transmit Data 0 | 7B | ETH_TXD1 | RGMII Transmit Data 1 | 7B | ETH_TXD2 | RGMII Transmit Data 2 | 7B | ETH_TXD3 | RGMII Transmit Data 3 | 7B | ETH_TXCTL | RGMII Transmit Control | 7B | ETH_RXCK | RGMII Receive Reference Clock | 7B | ETH_RXD0 | RGMII Receive Data 0 | 7B | ETH_RXD1 | RGMII Receive Data 1 | 7B | ETH_RXD2 | RGMII Receive Data 2 | 7B | ETH_RXD3 | RGMII Receive Data 3 | 7B | ETH_RXCTL | RGMII Receive Control | 7C | ETH_RST | Reset | 7B | ETH_MDC | Management Data Clock | 7B | ETH_MDIO | Management Data I/O | 7B | PHY_INT | Interrupt |
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High-Speed USB ULPI PHY
USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).
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anchor | Table_OBP_USB_PHY |
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title | USB PHY interface connections |
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orientation | portrait |
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PHY Pin | Connected to | Notes |
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ULPI | Intel Cyclone V HPS (U10) | -- | REFCLK | 24 MHz from on board oscillator (U34) | -- | REFSEL[0..2] | High (3.3 V) | -- | RESETB | Intel Cyclone V HPS (U10) and Intel MAX 10 (U41) | -- | DP, DM | 4-port USB 2.0 Hub (U33) | -- | CPEN | Not Connected. | -- | VBUS | Pull-up to 5 V. | -- | ID | Not Connected. | -- |
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4-Port USB 2.0 Hub
On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available (J2, J12). The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.
HDMI Transmitter
The TEI0022 board provides an HDMI interface routed to the Intel Cyclone FPGA (U10). The HDMI interface is created by the HDMI transmitter ADV7511 provided by Analog Devices. The HDMI transmitter is incorporated in conjunction with the HDMI protection circuit TI TPD12S016 for more signal robustness.
Scroll Title |
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anchor | Table_OBP_HDMI |
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title | HDMI connector signals and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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HDMI connector J11 | Signal Schematic Name | Connected to | Notes |
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Pin 1, 3 | HDMI_TX2_P / HDMI_TX2_N | HDMI transmitter, Pin 43, 42 | also connected to HDMI protection circuit | Pin 4, 6 | HDMI_TX1_P / HDMI_TX1_N | HDMI transmitter, Pin 40, 39 | also connected to HDMI protection circuit | Pin 7, 9 | HDMI_TX0_P / HDMI_TX0_N | HDMI transmitter, Pin 36, 35 | also connected to HDMI protection circuit | Pin 10, 12 | HDMI_TXC_P / HDMI_TXC_N | HDMI transmitter, Pin 33, 32 | also connected to HDMI protection circuit | Pin 13 | CEC_B | HDMI transmitter, Pin 48 | HDMI CEC, wired through HDMI protection circuit | Pin 15 | SCL_B | HDMI transmitter, Pin 53 | HDMI I²C clock line, wired through HDMI protection circuit | Pin 16 | SDA_B | HDMI transmitter, Pin 54 | HDMI I²C data line, wired through HDMI protection circuit | Pin 19 | HPD_B | HDMI transmitter, Pin 30 | Hot Plug Detect, wired through HDMI protection circuit | Pin 18 | 5V_HDMI | HDMI protection circuit, Pin 13 | 5V supply voltage, wired through HDMI protection circuit |
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FTDI (JTAG)
Please refer to the section "Micro USB Connector (JTAG)".
FTDI (UART)
Please refer to the section "Micro USB Connector (UART)".
DIP-Switches
There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
DIP-Switch S2
The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:
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anchor | Table_OBP_DIP_S2 |
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title | DIP-switch S2 functionality description |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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DIP-switch S2 | Position ON | Position OFF | Notes |
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S4-1 | HPS_SW1 is low | HPS_SW1 is high | User switch | S4-2 | HPS_SW2 is low | HPS_SW2 is high | User switch | S4-3 | FPGA_SW1 is low | FPGA_SW1 is high | User switch | S4-4 | FPGA_SW2 is low | FPGA_SW2 is high | User switch |
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DIP-Switch S7
The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:
Scroll Title |
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anchor | Table_OBP_DIP_S7 |
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title | DIP-switch S7 functionality description |
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