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id | Comments |
Important General Note:
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Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template:
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anchor | Figure_anchorname |
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title | Text |
Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
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anchor | Table_tablename |
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title | Text |
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The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
- type: Figure, Table
- main section:
- "OV" for Overview
- "SIP" for Signal Interfaces and Pins,
- "OBP" for On board Peripherals,
- "PWR" for Power and Power-On Sequence,
- "B2B" for Board to Board Connector,
- "TS" for Technical Specification
- "VCP" for Variants Currently in Production
- "RH" for Revision History
- name: custom, some fix names, see below
- Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
- "Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
- "Figure_RH_HRN" for Hardware_Revision_Number
- "Table_RH_DCH" for Document_Change_History
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Note for Download Link of the Scroll ignore macro:
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Table of Contents
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Overview
The Trenz Electronic TE0022-01 board is an industrial-grade SoC module based on Intel Cyclone V FPGA, an ethernet PHY, one GByte DDR3 SDRAM and one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.
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Notes :
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Short Link of the wiki resources reference:
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Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
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Key Features
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id | Comments |
Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options
Key Features' must be split into 6 main groups for modues:
- SoC/FPGA
- Package:
- Speed:
- Temperature:
- RAM/Storage
- E.g. SDRAM, SPI
- On Board
- E.g. CPLD, PLL
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
Key Features' must be split into 6 main groups for carrier:
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- TE0808, TE807, TE0803,...
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- E.g. SDRAM, SPI
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- E.g. CPLD, PLL
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- E.g. ETH, USB, B2B, Display port
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- E.g. Input supply voltage
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Create DrawIO object here: Attention if you copy from other page, objects are only linked.
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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Storage device name
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Content
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Notes
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HPS SPI Flash
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HPS Configuration
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Ethernet MAC
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Configuration Signals
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BOOTSEL[1..0] Signal State
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FPGA
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anchor | Table_OV_RST |
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title | Reset process. |
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Reset
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HPS cold reset
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Signals, Interfaces and Pins
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Notes :
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FMC LPC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
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anchor | Table_SIP_FMC |
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title | FMC connectors information |
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The FMC connector provides further interfaces like JTAG and I²C interfaces:
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anchor | Table_SIP_FMC_Interfaces |
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title | FMC connector pin-outs of available interfaces |
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FMC_TCK, Pin J4-D29
FMC_TMS, Pin J4-D33
FMC_TDI, Pin J4-D30
FMC_TDO, Pin J4- D31
FMC_TRST#, Pin J4- D34
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FMC_SCL, Pin J4-C30
FMC_SDA, Pin J4-C31
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FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V)
FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V)
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'PG' = 'Power Good'-signal
'C2M' = carrier to (Mezzanine) module
'M2C' = (Mezzanine) module to carrier
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JTAG Interface
According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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JTAGSEL1
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JTAGSEL1
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On-board Peripherals
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Notes :
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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Temperatur Sensor
The temperature sensor ADT7410 is implemented on the TEI0022 board.
Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA and the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
Quad SPI Flash memory U6 is connected to the HPS bank 7B and U15 to FPGA bank 3A.
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anchor | Table_OBP_QSPI_HPS |
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title | HPS Quad SPI interface signals and connections |
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anchor | Table_OBP_QSPI_FPGA |
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title | FPGA Quad SPI interface signals and connections |
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Programmable Clock Generator
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I2C
The TEI0022 provides two independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The other bus is used to handle the on-board I2C devices.
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anchor | Table_OBP_I2C |
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title | On-board peripherals' I2C-interfaces device slave addresses |
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IN1
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Not used
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IN3
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Reference input clock
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IN4
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IN5
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I²C interface muxed to FPGA
Slave address: 0x70.
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I²C interface muxed to FPGA
Slave address: 0x70.
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CLK0A/B
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CLK_B3B_p/n
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Clock to FPGA bank 3B
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CLK1A/B
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CLK_B4A_p/n
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Clock to FPGA bank 4A
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Clock to Intel MAX10 bank 2
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Oscillators
The FPGA module has following reference clocking source provided by an on-board oscillator:
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anchor | Table_OBP_OSC |
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title | Reference clock signals |
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System Controller Intel MAX10
The TEI0022 is equipped with an Intel MAX10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.
EEPROM
The TEI0022 board contains two EEPROMs for configuration and general user purposes.
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anchor | Table_OBP_EEPROM |
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title | On-board configuration EEPROMs overview |
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High-Speed USB ULPI PHY
USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).
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anchor | Table_OBP_USB_PHY |
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title | USB PHY interface connections |
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4-Port USB 2.0 Hub
On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available. The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.
Buttons
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DIP-Switches
There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
DIP-Switch S2
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DIP-Switch S7
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DIP-Switch S8
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On-Board LEDs
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA and HPS for storing user application code and data.
- Part number: IS43TR16512BL-125KBLI
- Supply voltage: 1.35 V
- Speed: ???
- Temperature: TC = -40 °C up to 95 °C
Gigabit Ethernet PHY
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ETH_TXCTL
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ETH_RXCTL
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Oscillators
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anchor | Table_OBP_CLK |
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title | Osillators |
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Power and Power-On Sequence
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id | Comments |
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
Power Supply
The maximum power consumption of this board mainly depends on the design which is running on the FPGA. Intel provides a power estimator excel sheets to calculate power consumption.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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* TBD - To Be Determined
Power Distribution Dependencies
All on-board voltages of the TEI0022 are generated out of the extern applied 12 V power supply.
There are following dependencies how the initial 12V power supply is distributed to the on-board DC-DC converters, which power up further DCDC converters and the particular on-board voltages:
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Power-On Sequence
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Power Rails
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anchor | Table_PWR_PR |
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title | Module power rails. |
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B2B Connector
JM1 Pin
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B2B Connector
JM2 Pin
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B2B Connector
JM3 Pin
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Bank Voltages
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Bank
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Voltage
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id | Comments |
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use "include page" macro and link to the general B2B connector page of the module series,
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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Currently Offered Variants
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anchor | Table_RH_DCH |
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title | Document change history. |
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change list
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all
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