Page History

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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoCXilinx Development Tools
• Vivado Projects - TE Reference Design
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
      2. For 128MB and 64MB only:Netboot Offset must be reduced manually, see Config
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

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Design specific constraint

Software Design - SDK/HSI

<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

SDK Projects

Application

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 2018.2 FSBL

• Changes:
  • enable VTC and VDMA cores (fsbl_hooks.c)

zynqmp_fsbl_flash

TE modified 2018.2 FSBL

Changes:

• Set FSBL Boot Mode to JTAG
• Disable Memory initialization

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

hello_te0726

Hello TE0726 is a Xilinx Hello World example as an endless loop instead of one console output and TE FSBL screen on HDMI Monitor.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Commands and actions used to create petalinux project

Code Block
language ruby title _i_common.xdc
# # # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Code Block
language ruby title _i_te0726.xdc
#set_property IOSTANDARD LVCMOS33 [get_ports spdif_tx_o] #set_property PACKAGE_PIN K15 [get_ports spdif_tx_o] set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_1_tri_io[*]}] # GPIO Pins # GPIO2 set_property PACKAGE_PIN K15 [get_ports {GPIO_1_tri_io[0]}] # GPIO3 set_property PACKAGE_PIN J14 [get_ports {GPIO_1_tri_io[1]}] # GPIO4 set_property PACKAGE_PIN H12 [get_ports {GPIO_1_tri_io[2]}] # GPIO5 set_property PACKAGE_PIN N14 [get_ports {GPIO_1_tri_io[3]}] # GPIO6 set_property PACKAGE_PIN R15 [get_ports {GPIO_1_tri_io[4]}] # GPIO7 set_property PACKAGE_PIN L14 [get_ports {GPIO_1_tri_io[5]}] # GPIO8 set_property PACKAGE_PIN L15 [get_ports {GPIO_1_tri_io[6]}] # GPIO9 set_property PACKAGE_PIN J13 [get_ports {GPIO_1_tri_io[7]}] # GPIO10 set_property PACKAGE_PIN H14 [get_ports {GPIO_1_tri_io[8]}] # GPIO11 set_property PACKAGE_PIN J15 [get_ports {GPIO_1_tri_io[9]}] # GPIO12 set_property PACKAGE_PIN M15 [get_ports {GPIO_1_tri_io[10]}] # GPIO13 set_property PACKAGE_PIN R13 [get_ports {GPIO_1_tri_io[11]}] # GPIO16 set_property PACKAGE_PIN L13 [get_ports {GPIO_1_tri_io[12]}] # GPIO17 set_property PACKAGE_PIN G11 [get_ports {GPIO_1_tri_io[13]}] # GPIO18 set_property PACKAGE_PIN H11 [get_ports {GPIO_1_tri_io[14]}] # GPIO19 set_property PACKAGE_PIN R12 [get_ports {GPIO_1_tri_io[15]}] # GPIO20 set_property PACKAGE_PIN M14 [get_ports {GPIO_1_tri_io[16]}] # GPIO21 set_property PACKAGE_PIN P15 [get_ports {GPIO_1_tri_io[17]}] # GPIO22 set_property PACKAGE_PIN H13 [get_ports {GPIO_1_tri_io[18]}] # GPIO23 set_property PACKAGE_PIN J11 [get_ports {GPIO_1_tri_io[19]}] # GPIO24 set_property PACKAGE_PIN K11 [get_ports {GPIO_1_tri_io[20]}] # GPIO25 set_property PACKAGE_PIN K13 [get_ports {GPIO_1_tri_io[21]}] # GPIO26 set_property PACKAGE_PIN L12 [get_ports {GPIO_1_tri_io[22]}] # GPIO27 set_property PACKAGE_PIN G12 [get_ports {GPIO_1_tri_io[23]}] ## DSI_D0_N #set_property PACKAGE_PIN F13 [get_ports {GPIO_1_tri_io[24]}] ## DSI_D0_P #set_property PACKAGE_PIN F14 [get_ports {GPIO_1_tri_io[25]}] ## DSI_D1_N #set_property PACKAGE_PIN F12 [get_ports {GPIO_1_tri_io[26]}] ## DSI_D1_P #set_property PACKAGE_PIN E13 [get_ports {GPIO_1_tri_io[27]}] ## DSI_C_N #set_property PACKAGE_PIN E11 [get_ports {GPIO_1_tri_io[28]}] ## DSI_C_P #set_property PACKAGE_PIN E12 [get_ports {GPIO_1_tri_io[29]}] ## CSI_D0_N #set_property PACKAGE_PIN M11 [get_ports {GPIO_1_tri_io[30]}] ## CSI_D0_P #set_property PACKAGE_PIN M10 [get_ports {GPIO_1_tri_io[31]}] ## CSI_D1_N #set_property PACKAGE_PIN P14 [get_ports {GPIO_1_tri_io[32]}] ## CSI_D2_P #set_property PACKAGE_PIN P13 [get_ports {GPIO_1_tri_io[33]}] ## CSI_C_N #set_property PACKAGE_PIN N12 [get_ports {GPIO_1_tri_io[34]}] ## CSI_C_P #set_property PACKAGE_PIN N11 [get_ports {GPIO_1_tri_io[35]}] ## PWM_R ##set_property PACKAGE_PIN N8 [get_ports {GPIO_1_tri_io[36]}] ## PWM_L ##set_property PACKAGE_PIN N7 [get_ports {GPIO_1_tri_io[37]}] # PWM_R set_property PACKAGE_PIN N8 [get_ports PWM_R] # PWM_L set_property PACKAGE_PIN N7 [get_ports PWM_L] set_property IOSTANDARD LVCMOS33 [get_ports PWM_*]

Code Block
language ruby title _i_hdmi.xdc
set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p] set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[*]}] set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}] set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}] set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}]

Code Block
language ruby title _i_csi.xdc
set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p] set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p] set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}] set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}] set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}] set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}] set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}] set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}] set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}] set_property INTERNAL_VREF 0.6 [get_iobanks 34] set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}] set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}] # RPI Camera 1 create_clock -period 6.250 -name csi_clk -add [get_ports csi_c_clk_p] # RPI Camera 2.1 #create_clock -period 1.875 -name csi_clk -add [get_ports csi_c_clk_p]

Code Block
language ruby title _i_timing.xdc
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/tx_sync/out_data_reg[4]}] set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/SDATA_O_reg[0]}] set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_3] set_false_path -from [get_clocks clk_fpga_3] -to [get_clocks clk_fpga_0] set_false_path -from [get_pins {zsys_i/axi_reg32_0/U0/axi_reg32_v1_0_S_AXI_inst/slv_reg16_reg[1]/C}] -to [get_pins zsys_i/video_in/axis_raw_demosaic_0/U0/colors_mode_i_reg/D] set_false_path -from [get_pins zsys_i/video_in/csi_to_axis_0/U0/lane_align_inst/err_req_reg/C] -to [get_pins zsys_i/video_in/csi2_d_phy_rx_0/U0/clock_upd_req_reg/D] set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_max_first_increment_reg[2]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D] set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]

Software Design - SDK/HSI

<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

SDK Projects

Application

SDK template in ./sw_lib/sw_apps/ available.

zynq_fsbl

TE modified 2018.2 FSBL

• Changes:
  • enable VTC and VDMA cores (fsbl_hooks.c)

zynq_fsbl_flash

TE modified 2018.2 FSBL

Changes:

• Set FSBL Boot Mode to JTAG
• Disable Memory initialization

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

hello_te0726

Hello TE0726 is a Xilinx Hello World example as an endless loop instead of one console output and TE FSBL screen on HDMI Monitor.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart
• petalinux-create -t project -n petalinux --template zynq
• copy hdf file to petalinux directory
• cd petalinux
• petalinux-config --get-hw-description
• leave default configuration and select "<Exit>"
• petalinux-create -t apps -n startup --enable
• copy/create startup app files
• petalinux-create -t apps -n rpicam --enable
• copy/create rpicam app files
• petalinux-create -t modules -n te-audio-codec --enable
• copy/create te-audio-codec module files
• copy/modify project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
• petalinux-config -c rootfs
• Enable Filesystem Packages → Base → i2c-tools → i2c-tools and other apps needed for your system
• Save configuration and exit config
• petalinux-config -c kernel
  
  • CONFIG_USB_USBNET
  • CONFIG_USB_NET_SMSC95XX
  • CONFIG_USBIP_CORE
  • CONFIG_FB_SIMPLE
  • SND_SIMPLE_CARD
  • CONFIG_SND_SOC_ADI_AXI_I2S
• petalinux-build

Config

For 64MB variant only:

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Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\\project-spec\meta-user\recipes-apps\startup\files

Add on new project:

• petalinux-create -t apps -n startup --enable
• copy/create startup app files

rpicam

Application used to enable and configure Raspbery Pi camera module

See: \os\petalinux\project-spec\meta-user\recipes-apps\rpicam\files

Add on new project:

• petalinux-create -t apps -n rpicam --enable
• copy/create rpicam app files

Kernel Modules

te-audio-codec

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See: \os\petalinux\project-spec\meta-user\recipes-modules\te-audio-codec\files

Add on new project:

• petalinux-create -t modules -n te-audio-codec --enable
• copy/create te-audio-codec module files

Additional Software

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