Page History
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- SoC/FPGA
- Xilinx UltraScale+ RFSoC (XCZU25DR-1FFVE1156E)
- Package: E1156
- Speed: -1 (slowest)
- Temperature: Extended (0 to +100 °C)
- Xilinx UltraScale+ RFSoC (XCZU25DR-1FFVE1156E)
- RAM/Storage
- 4x 8Gb DDR4
- 2x 512Mb SPI Flash
- On Board
- Lattice iCE40 MachXO2 CPLD
- Programmable Clock Generator
- 3x Oscillators
- Interface
- 2x Samtec ST5 (2x80 pol) Board to Board Connectors
- Power
- 5V Input Supply Voltage
- Dimension
- 90 x 65 mm
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- Xilinx UltraScale+ MPSoC XCZU25DR, U1
- 8Gb DDR4 SDRAM, U2,U3,U5,U9
- Voltage Regulators, U4,U6,U7
- Programmable Glock Generator, U15
- Lattice MachXO2 CPLD, U31
- ...
- Dual SPI Flash, U24-U25
- USB2.0 Transceiver, U11
- Pin Header 3x1, J3 (not Soldered)
- Gigabit Ethernet Transceiver, U20
- EEPROM, U23
- B2B Connector, J2
- B2B Connector, J1...
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example:
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Overview
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