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| Page properties |
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- Overview of Boot Mode, Reset, Enables.
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Configuration must be set through CPLD by setting MODE0...3 signals.
| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| scroll-tablelayout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE Signal State | Boot Mode |
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| tablelayout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE[0:3] | Boot Mode | Connected to | Note |
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0000 | PS_JTAG | JTAG | PSJTAG Interface |
| 0001 | Quad SPI (24b) | MIO0...12 | QSPI 24bit addressing |
| 0010 | Quad SPI (32b) | MIO0...12 | QSPI 32bit addressing |
| 0011 | SD0 2.0 | MIO13...25 | SD 2.0 |
| 0100 | NAND |
| Requires 8 bit data bus width |
| 0101 | SD1 2.0 |
| SD 2.0 |
| 0110 | eMMC |
| eMMC version 4.5 at 1.8 V |
| 0111 | USB2.0 |
| Only USB2.0 |
| 1000 | PJTAG |
| PJTAG Connection 0 0ption |
| 1001 | PJTAG |
| PJTAG Connection 1 0ption |
| 1110 | SD1 LS 3.0 |
| SD 3.0 with complaint voltage level shifter |
| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | B2B | I/O | Note |
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RESETN | J1-36 | Input | Pulled up to 3.3V_CPLD |
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Signals, Interfaces and Pins
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