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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TE0835 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 23 |
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| diagramName | TE0835_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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B2B ConnectorInterface| B2B Connector | Number of I/Os | Voltage Level | Notes |
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JTAG access to the TExxxx SoM through B2B connector JMX.
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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| 500 | J1 | 12x Single Ended | 1.8V | MIO14...25 | | 501 | J1 | 20x Single Ended | 1.8V | MIO26...51 | | 505 | J1 | 18x Single Ended, 9x Differential pairs | 0.85V | EXT_CLKIN_PSMGT, RX/TX0...3 | | 128 | J1 | 18x Single Ended, 9x Differential pairs | 0.9V | B128_CLK, RX/TX0...3 | | 129 | J1 | 18x Single Ended, 9x Differential pairs | 0.9V | B129_CLK, RX/TX0...3 | | 65 | J2 | 24x Single Ended, 12x Differential pairs | 1.8V |
| | 88 | J2 | 16x Single Ended, 8x Differential pairs | 3.3V | HD_B88 |
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JTAG Interface
JTAG access to the TE0835 is through B2B connector JM1.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector |
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| JTAG_TMS | J1-24 | | JTAG_TDI | J1-20 | | JTAG_TDO | J1-18 | | JTAG_TCK | J1-22 |
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MIO Pins
| Page properties |
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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| Scroll Title |
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| anchor | Table_OBP_MIOs |
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| title | MIOs pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Connected to | B2B | Notes |
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| MIO0...12 | SPI FLash, U24-U25 | - | Dual SPI FLash | | MIO13 | LED Green, D1 | - | 3.3V_CPLD | | MIO14...25 | FPGA Bank 500,U1 | J1 | PSMIO | | MIO26...27 | FPGA Bank 501,U1 | J1 | PSMIO | | MIO28...29 | CPLD, U31 | - | UART_TX, UART_RX | | MIO30...31 | FPGA Bank 501, U1 | J1 | PSMIO | | MIO32...33 | EEPROM,U23 | - | I2C_SCL, I2C_SDA | | MIO34...35 | FPGA Bank 501,U1 | J1 | PSMIO | | MIO36 | Gigabit ETH, U20 | - | ETH_RST | | MIO37 | USB2.0, U11 | - | USB_RST | | MIO38...51 | FPGA Bank 501, U1 | J1 | PSMIO | | MIO52...62 | USB2.0, U11 | - | USB | | MIO63...77 | Gigabit ETH, U20 | - | ETH |
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Test Points
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| Page properties |
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you must fill the table below with group of MIOs Test Point which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematicindicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: | Test Point | Signal | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI | | 10 | PWR_PL_OK | J2-120 |
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| Scroll Title |
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| anchor | Table_OBPSIP_MIOsTPs |
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| title | MIOs pinsTest Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Page properties |
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
| CLKOUT | Voltage Regulator, U7 |
| | TP2 | PLL_RSTN | Programmable Clock Generator, U15 |
| | TP3 | 3.3V_CPLD |
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| | TP4 | CPLD_JTAGEN |
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| | TP5 | JTAG_TDO |
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| | TP6 | JTAG_TDI |
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| | TP7 | JTAG_TCK |
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| | TP8 | JTAG_TMS |
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| | TP9 | GND |
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| | TP10...11 | IO_L1P_AD15P_88, O_L4N_AD12N_88 | FPGA Bank 88, U1 |
| | TP12 | VIN | B2B, J1 |
| | TP13...14 | GND |
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| | TP15...16 | MIO32-MIO33 | EEPROM,U23 FPGA Bank 501, U1 |
| | TP17 | GND |
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| | TP18 | ADC_AVCC | LDO Voltage Regulator, U8 |
| | TP19 | ADC_AVCCAUX | LDO Voltage Regulator, U10 |
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| Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 | | Scroll Title |
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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On-board Peripherals
| Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | Designator | Notes |
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| SPI Flash | U24, U25 |
| | DDR4 SDRAM | U2, U3, U5, U9 |
| | CPLD | U31 |
| | USB2.0 | U11 |
| | Gigabit Ethernet | U20 |
| | Programmable Clock Generator | U15 |
| | EEPROM | U22 |
| | Oscillators | U14, U21, U12 |
| | LEDs | D0...7 |
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Quad SPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? U24 Pin | Notes |
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RTC
| Scroll Title |
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| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U? Pin | Notes |
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