| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Test Point | Signal | Connected to | Notes |
|---|
| TP1 | CLKOUT | Voltage Regulator, U7 |
| | TP2 | PLL_RSTN | Programmable Clock Generator, U15 |
| | TP3 | 3.3V_CPLD | B2B, J1 |
| | TP4 | CPLD_JTAGEN | B2B, J1 CPLD, U31 |
| | TP5 | JTAG_TDO | B2B, J1 CPLD, U31 |
| | TP6 | JTAG_TDI | B2B, J1 CPLD, U31 |
| | TP7 | JTAG_TCK | B2B, J1 CPLD, U31 |
| | TP8 | JTAG_TMS | B2B, J1 CPLD, U31 |
| | TP9 | GND | GND |
| | TP10...11 | IO_L1P_AD15P_88, O_L4N_AD12N_88 | FPGA Bank 88, U1 |
| | TP12 | VIN | B2B, J1 |
| | TP13...14 | GND | GND |
| | TP15...16 | MIO32-MIO33 | EEPROM,U23 FPGA Bank 501, U1 |
| | TP17 | GND | GND |
| | TP18 | ADC_AVCC | LDO Voltage Regulator, U8 |
| | TP19 | ADC_AVCCAUX | LDO Voltage Regulator, U10 |
|
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