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| Scroll Title |
|---|
| anchor | Table_OBP |
|---|
| title | On board peripherals |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
...
| Scroll Title |
|---|
| anchor | Table_OBP_SPI |
|---|
| title | Quad SPI interface MIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| MIO Pin | Schematic | U24 Pin | U25 Pin | Notes |
|---|
| MIO0 | MIO0_QSPI | CLK | - |
| | MIO1 | MIO1_QSPI | DO | - |
| | MIO2 | MIO2_QSPI | nWP | - |
| | MIO3 | MIO3_QSPI | nHOLD | - |
| | MIO4 | MIO4_QSPI | DI | - |
| | MIO5 | MIO5_QSPI | nCS | - |
| | MIO7 | MIO5_QSPI | - | nCS |
| | MIO8 | MIO5_QSPI | - | DI |
| | MIO9 | MIO5_QSPI | - | DO |
| | MIO10 | MIO5_QSPI | - | nWP |
| | MIO11 | MIO5_QSPI | - | nHOLD |
| | MIO12 | MIO5_QSPI | - | CLK |
|
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System Controller CPLD
The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG / UART and I2C between the on-board peripherals and the attached module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and the programming state of the attached module.
| Scroll Title |
|---|
| anchor | Table_OBP_USB |
|---|
| title | USB2.0 interface connections and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic/Pin | Connected to | Description | Note |
|---|
| MODE0...3 | FPGA Bank 503, U1 | Boot Mode |
| | POR_B | FPGA Bank 503, U1 | Programming Status | Pulled up | | PORG_B | FPGA Bank 503, U1 | Programming Status | Pulled up | | INIT_B | FPGA Bank 503, U1 | Configuration initialization | Pulled up | | DONE | FPGA Bank 503, U1 | Configuration Done Status | Pulled up | | F_TCK | FPGA Bank 503, U1 | FPGA JTAG |
| | F_TDI | FPGA Bank 503, U1 | FPGA JTAG |
| | F_TMS | FPGA Bank 503, U1 | FPGA JTAG |
| | F_TDO | FPGA Bank 503, U1 | FPGA JTAG |
| | JTAG_TDO | B2B, J1 | CPLD JTAG |
| | JTAG_TMS | B2B, J1 | CPLD JTAG |
| | JTAG_TDI | B2B, J1 | CPLD JTAG |
| | JTAG_TCK | B2B, J1 | CPLD JTAG |
| | CPLD_JTAGEN | B2B, J1 | CPLD JTAG Enable |
| | CPLDIO0...3 | B2B, J1 | CPLD IOs |
| | RESETN | B2B, J1 | Reset |
| | MIO13 | LED Green, D1 | 3.3V_CPLD |
| | MIO28 | FPGA Bank 501, U1 | UART_TX |
| | MIO29 | FPGA Bank 501, U1 | UART_RX |
| | FPGA_IO0...1 | FPGA Bank 65, U1 | IOs |
| | EN_PS_PL | Voltage Regulators, U6, U7, U29 | PS/PL Enable Signals | Pulled Down | | EN_GR1 | Voltage Regulators, U19, U27, U28 | MGTAVTT, PSLL | Pulled Down | | EN_GR2 | Voltage Regulators, U38, U18, U38 | PS_MGTRAVTT, 3.3, DDR2.5V | Pulled Down | | EN_RF_ADC | Voltage Regulators, U8 | Enable ADC | Pulled Down | | PG_RF_DAC | Voltage Regulators, U17 | ADC Power Good Status | Pulled Down | | PG_PS_PL | Voltage Regulators, U6, U7, U29 | PS/PL Power Good Status | Pulled Down | | EN_RF_DAC | Voltage Regulators, U13 | Enable DAC | Pulled Down | | PG_RF_DAC | Voltage Regulators, U10 | DAC Power Good Status | Pulled Down |
|
USB2.0
The TE0835 is equipped with a USB2.0, U11.
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