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anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

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MIO Pin	Schematic	U24 Pin	U25 Pin
MIO0	MIO0_QSPI	CLK	-
MIO1	MIO1_QSPI	DO	-
MIO2	MIO2_QSPI	nWP	-
MIO3	MIO3_QSPI	nHOLD	-
MIO4	MIO4_QSPI	DI	-
MIO5	MIO5_QSPI	nCS	-
MIO7	MIO5_QSPI	-	nCS
MIO8	MIO5_QSPI	-	DI
MIO9	MIO5_QSPI	-	DO
MIO10	MIO5_QSPI	-	nWP
MIO11	MIO5_QSPI	-	nHOLD
MIO12	MIO5_QSPI	-	CLK

System Controller CPLD

The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG / UART and I²C between the on-board peripherals and the attached module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and the programming state of the attached module.

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title	USB2.0 interface connections and pins

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Schematic/Pin	Connected to	Description	Note
MODE0...3	FPGA Bank 503, U1	Boot Mode
POR_B	FPGA Bank 503, U1	Programming Status	Pulled up
PORG_B	FPGA Bank 503, U1	Programming Status	Pulled up
INIT_B	FPGA Bank 503, U1	Configuration initialization	Pulled up
DONE	FPGA Bank 503, U1	Configuration Done Status	Pulled up
F_TCK	FPGA Bank 503, U1	FPGA JTAG
F_TDI	FPGA Bank 503, U1	FPGA JTAG
F_TMS	FPGA Bank 503, U1	FPGA JTAG
F_TDO	FPGA Bank 503, U1	FPGA JTAG
JTAG_TDO	B2B, J1	CPLD JTAG
JTAG_TMS	B2B, J1	CPLD JTAG
JTAG_TDI	B2B, J1	CPLD JTAG
JTAG_TCK	B2B, J1	CPLD JTAG
CPLD_JTAGEN	B2B, J1	CPLD JTAG Enable
CPLDIO0...3	B2B, J1	CPLD IOs
RESETN	B2B, J1	Reset
MIO13	LED Green, D1	3.3V_CPLD
MIO28	FPGA Bank 501, U1	UART_TX
MIO29	FPGA Bank 501, U1	UART_RX
FPGA_IO0...1	FPGA Bank 65, U1	IOs
EN_PS_PL	Voltage Regulators, U6, U7, U29	PS/PL Enable Signals	Pulled Down
EN_GR1	Voltage Regulators, U19, U27, U28	MGTAVTT, PSLL	Pulled Down
EN_GR2	Voltage Regulators, U38, U18, U38	PS_MGTRAVTT, 3.3, DDR2.5V	Pulled Down
EN_RF_ADC	Voltage Regulators, U8	Enable ADC	Pulled Down
PG_RF_DAC	Voltage Regulators, U17	ADC Power Good Status	Pulled Down
PG_PS_PL	Voltage Regulators, U6, U7, U29	PS/PL Power Good Status	Pulled Down
EN_RF_DAC	Voltage Regulators, U13	Enable DAC	Pulled Down
PG_RF_DAC	Voltage Regulators, U10	DAC Power Good Status	Pulled Down

USB2.0

The TE0835 is equipped with a USB2.0, U11.

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title	USB2.0 interface connections and pins

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U11 Pin	Schematic	Connected to
RESETB	USB0_RST	FPGA Bank 501, U1
VDDIO	1.8V	1.8V
CPEN	USB0_CPE	B2B, J1
VBUS	USB0_VBUS	B2B, J1
ID	USB0_ID	B2B, J1
DP	USB0_D_P	B2B, J1
DM	USB0_D_N	B2B, J1
REFCLK	USB_CLK	Oschillator, U12
STP	USB0_STP	FPGA Bank 502, U1
NXT	USB0_NXT	FPGA Bank 502, U1
DIR	USB0_DIR	FPGA Bank 502, U1
CLKOUT	USB_CLK	Oschillator, U12
DATA0...7	USB0_DATA0...8	FPGA Bank 502, U1

Ethernet

The module TE0835 is equipped with a Gigabit Ethernet Transceiver, U20.

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title	Ethernet connections

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U20 Pin	Signal Name	Connected to	Signal Description
MDIO	ETH_MDIO	FPGA Bank 502, U1	Data Management
MDC	ETH_MDC	FPGA Bank 502, U1	Data Management clock reference for the serial interface
TX_CLK	ETH_TXCK	FPGA Bank 502, U1	Transmit Clock
TX_CTRL	ETH_TXCTL	FPGA Bank 502, U1	Transmit Control
TXD0...3	ETH_TXD0...3	FPGA Bank 502, U1	Transmit Data
RX_CLK	ETH_RXCK	FPGA Bank 502, U1	Receive Clock
RX_CTRL	ETH_RXCTL	FPGA Bank 502, U1	Receive Control
RXD0...3	ETH_RXD0...3	FPGA Bank 502, U1	Receive Data
RESETn	ETH_RST	FPGA Bank 501, U1	Ethernet reset, Active low.
XTAL_IN	ETH_XTAL_IN	Oscillator, U21	Reference Clock
MDI0...3	PHY_MDI0...3	B2B, J1	Media Dependent Interface 0...3
LED0...1	PHY_LED0...1	B2B, J1	LED output
LED/INT	PHY_LED2	B2B, J1	LED interrupt

EEPROM

The module TE0835 has an EEPROM (U23) connected to PSMIO FPGA Bank 501.

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title	On-board LEDs

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Designator	Color	Connected to	Active Level
D1	Green	MIO13	Active High
D2...5	Red	DBG_LED0...3	Active Low
D6	Red	ERR_OUT	Active High
D7	Red	ERR_STATUS	Active High

DDR4 SDRAM

Page properties

hidden	true
id	Comments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

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anchor	Table_OBP_PCLK
title	Programmable Clock Generator Inputs and Outputs

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U15 Pin	Signal	Connected to	Direction	Note
IN0	IN0_P	Oscillator, U14	Input
IN1	-	N.C	-
IN2	EXT_CLK_IN1	B2B,J2	Input
IN3	-	N.C
nRST	PLL_RSTN	FPGA Bank 65,U1	Input
SCL	MIO32_I2C1_SCL	Pin Header, J3	Input
SDA	MIO33_I2C1_SDA	Pin Header, J3	Input
OUT0...5	CLKA...F	B2B,J2	Output	6x Differential Clocks
OUT6	B128_CLK0	FPGA Bank 128,U1	Output
OUT7	B129_CLK0	FPGA Bank 129,U1	Output
OUT8	CLK8	FPGA Bank 65,U1	Output
OUT9	PSMGT_100MHZ	FPGA Bank 505,U1	Output
OUT9A	CLK0A_100MHZ	B2B, J1	Output

Power and Power-On Sequence

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Trenz Electronic Documentation

Versions Compared

Old Version 21

New Version 22

Key

System Controller CPLD

USB2.0

Ethernet

EEPROM

DDR4 SDRAM

Power and Power-On Sequence