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The Trenz Electronic TE0835 is an extended-grade module based on Xilinx Zynq UltraScale+ RFSoC.  The module is equipped with 4x 8Gb DDR4 SDRAM Memory, 2x 512Mb SPI Flash Memory, USB2.0, Ethernet Transceiver and 2x Samtec Razor Beam Borard to Board (B2B) Connectors. The system controller CPLD is provided by Lattice MachXO2.

The Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bitquad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system. 

Refer to http://trenz.org/te0835-info for the current online version of this manual and other available documentation.

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titleTE0835 block diagram


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titleTest Points Information

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Test PointSignalConnected toNotes
TP1CLKOUTVoltage Regulator, U7
TP2PLL_RSTNProgrammable Clock Generator, U15
TP33.3V_CPLDB2B, J1
TP4CPLD_JTAGEN

B2B, J1

CPLD, U31


TP5JTAG_TDO

B2B, J1

CPLD, U31


TP6JTAG_TDI

B2B, J1

CPLD, U31


TP7JTAG_TCK

B2B, J1

CPLD, U31


TP8JTAG_TMS

B2B, J1

CPLD, U31


TP9GNDGND
TP10...11

IO_L1P_AD15P_88, 

O_L4N_AD12N_88

FPGA Bank 88, U1
TP12VINB2B, J1
TP13...14GNDGND
TP15...16MIO32-MIO33

EEPROM,U23

FPGA Bank 501, U1


TP17GNDGND
TP18ADC_AVCCLDO Voltage Regulator, U8
TP19ADC_AVCCAUXLDO Voltage Regulator, U10



On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
SPI FlashU24, U25
DDR4 SDRAMU2, U3, U5, U9
CPLDU31
USB2.0U11
Gigabit EthernetU20
Programmable Clock GeneratorU15
EEPROMU22
OscillatorsU14, U21, U12
LEDsD0...7


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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titleQuad SPI interface MIOs and pins

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MIO PinSchematicU24 PinU25 PinNotes
MIO0MIO0_QSPICLK-
MIO1MIO1_QSPIDO-
MIO2MIO2_QSPInWP-
MIO3MIO3_QSPInHOLD-
MIO4MIO4_QSPIDI-
MIO5MIO5_QSPInCS-
MIO7MIO5_QSPI-nCS
MIO8MIO5_QSPI-DI
MIO9MIO5_QSPI-DO
MIO10MIO5_QSPI-nWP
MIO11MIO5_QSPI-nHOLD
MIO12MIO5_QSPI-CLK


System Controller CPLD

The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG / UART and I2C between the on-board peripherals and the attached module are by-passed, forwarded and controlled by the System Controller CPLD.

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titleUSB2.0 interface connections and pins

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Schematic/PinConnected toDescriptionNote
MODE0...3FPGA Bank 503, U1Boot Mode
POR_BFPGA Bank 503, U1Programming StatusPulled up
PORG_BFPGA Bank 503, U1Programming StatusPulled up
INIT_BFPGA Bank 503, U1Configuration initializationPulled up
DONEFPGA Bank 503, U1Configuration Done StatusPulled up
F_TCKFPGA Bank 503, U1FPGA JTAG
F_TDIFPGA Bank 503, U1FPGA JTAG
F_TMSFPGA Bank 503, U1FPGA JTAG
F_TDOFPGA Bank 503, U1FPGA JTAG
JTAG_TDOB2B, J1CPLD JTAG
JTAG_TMSB2B, J1CPLD JTAG
JTAG_TDIB2B, J1CPLD JTAG
JTAG_TCKB2B, J1CPLD JTAG
CPLD_JTAGENB2B, J1CPLD JTAG Enable
CPLDIO0...3B2B, J1CPLD IOs
RESETNB2B, J1Reset
MIO13LED Green, D13.3V_CPLD
MIO28FPGA Bank 501, U1UART_TX
MIO29FPGA Bank 501, U1UART_RX
FPGA_IO0...1FPGA Bank 65, U1IOs
EN_PS_PLVoltage Regulators, U6, U7, U29PS/PL Enable SignalsPulled Down
EN_GR1Voltage Regulators, U19, U27, U28MGTAVTT, PSLL Pulled Down
EN_GR2Voltage Regulators, U38, U18, U38PS_MGTRAVTT, 3.3, DDR2.5VPulled Down
EN_RF_ADCVoltage Regulators, U8Enable ADCPulled Down
PG_RF_DACVoltage Regulators, U17ADC Power Good Status Pulled Down
PG_PS_PLVoltage Regulators, U6, U7, U29PS/PL Power Good Status Pulled Down
EN_RF_DACVoltage Regulators, U13Enable DACPulled Down
PG_RF_DACVoltage Regulators, U10DAC Power Good Status Pulled Down


USB2.0

The TE0835 is equipped with a USB2.0, U11. 

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U11 PinSchematicConnected toNotes
RESETBUSB0_RSTFPGA Bank 501, U1
VDDIO1.8V1.8V
CPENUSB0_CPEB2B, J1
VBUSUSB0_VBUSB2B, J1
IDUSB0_IDB2B, J1
DPUSB0_D_PB2B, J1
DMUSB0_D_NB2B, J1
REFCLKUSB_CLKOschillator, U12
STPUSB0_STPFPGA Bank 502, U1
NXTUSB0_NXTFPGA Bank 502, U1
DIRUSB0_DIRFPGA Bank 502, U1
CLKOUTUSB_CLKOschillator, U12
DATA0...7USB0_DATA0...8FPGA Bank 502, U1


Ethernet

The module TE0835 is equipped with a Gigabit Ethernet Transceiver, U20.

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U20 PinSignal NameConnected toSignal DescriptionNote
MDIOETH_MDIOFPGA Bank 502, U1Data Management
MDCETH_MDCFPGA Bank 502, U1Data Management clock reference for the serial interface
TX_CLKETH_TXCKFPGA Bank 502, U1Transmit Clock
TX_CTRLETH_TXCTLFPGA Bank 502, U1Transmit Control
TXD0...3ETH_TXD0...3FPGA Bank 502, U1Transmit Data
RX_CLKETH_RXCKFPGA Bank 502, U1Receive Clock
RX_CTRLETH_RXCTLFPGA Bank 502, U1Receive Control
RXD0...3ETH_RXD0...3FPGA Bank 502, U1Receive Data
RESETnETH_RSTFPGA Bank 501, U1Ethernet reset, Active low.
XTAL_INETH_XTAL_INOscillator, U21Reference Clock

MDI0...3

PHY_MDI0...3B2B, J1Media Dependent Interface 0...3
LED0...1PHY_LED0...1B2B, J1LED output
LED/INTPHY_LED2B2B, J1LED interrupt


EEPROM

The module TE0835 has an EEPROM (U23) connected to PSMIO FPGA Bank 501.

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titlePower Distribution


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titleModule power rails.

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JM1
Power Rail Name

B2B Connector

B2B  J1 Pin

B2B Connector

JM2

B2B  J2 Pin

DirectionNotes
VIN1,2,3,4,5,6,8-Input
PSBATT14-Input
3.3V_CPLD16-Output


Bank Voltages

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titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes
Bank 65 HPVCCO_651.8V
Bank 503 PSCONFIG

VCCO_PSIO3_503

1.8V
Bank 88 HDVCCO_883.3V
BANK 128 GTHMGTAVCC0.9V
BANK 129 GTHMGTAVCC0.9V
BANK 500 PSMIOVCCO_PSIO0_5001.8V
BANK 501 PSMIOVCCO_PSIO0_5011.8V
BANK 502VCCO_PSIO0_5021.8V
BANK 504 PSDDRVCCO_PSDDR_5041.2V
BANK 505 PSGTRPS_MGTRAVCC0.85V



Board to Board Connectors

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SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage05V
T_STGStorage Temperature-40100°C


Recommended Operating Conditions

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