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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

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Table of Contents

Table of Contents

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The Trenz Electronic TEI0023 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to httpshttp://wiki.trenz-electronic.de/display/PD/TEI0023+Resourcesorg/tei0023-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features' must be split into 6 main groups for modules and mainboards:

SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
RAM/Storage
- Low Power DDR4 on PS
  - Data width: 32bit
  - Size: def. 2GB*
  - Speed:***
- eMMC
  - Data width: 8Bit
  - size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
  - Data width: 8bit
  - size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
  - size:*
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
Dimension
- 4 cm x 5 cm
Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination

Key Features' must be split into 6 main groups for carrier:

Modules
- TE0808, TE807, TE0803,...
RAM/Storage
- E.g. SDRAM, SPI
On Board
- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

Intel® MAX 10 Commercial FPGA [10M08SAU169C8G]
- Package: UBGA-169
- Speed Grade: C8 (Slowest)
- Temperature: 0°C to 85°C (Commercial)
- Package compatible device 10M02.10M08..10M16 as assembly variant on request possible
SDRAM Memory up to 64Mb, 166MHz32 Mbyte (8Mbyte default)
USB 2.0 Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mb Quad SPI Flash - No on all variants
4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
(FT2232H)
- 4 Kbit EEPROM Memory for FTDI configuration data
- Micro USB Receptacle (communication and power)
SPI Flash - NOT INSTALLED (only special option)
8x User LED's
18 Bit 2 MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO - Arduino MKR compatible
Power Supply: 5V
Dimension: 86.5mm x 25mm
Fully-Differential Programmable-Gain Instrumentation Amplifier

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draw.io Diagram

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SMA Connector, J5...6
Amplifier, U12
Series Voltage Reference, U8
Analog to Digital Converter, U6
Voltage Regulator, U4 - U10 - U13 - U16
Switching Voltage Regulator, U11
SDRAM Memory, U2
Intel® MAX 10 FPGA, U1
SPI Flash Memory, U5 (not populated)
Oscillator, U7 - U19
FTDI USB2 USB to JTAG/UART FIFO Adapter, U3
User LEDs, D2...9
FTDI Configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-On LED (Green), D1
Push Button, S1...2
Micro USB Connector, J9
1x14 Pin Header, J2 (Not assembled)
1x6 Pin Header, J4 (Not assembled)
1x4 Pin Header, J3 (Not assembled)
1x14 Pin Header, J1 (Not assembled)

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Notes :

Only components like EEPROM, QSPI SPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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SDRAM

Storage device name

Content

Notes

Quad SPI Flash

N/A

Not

Programmed

populated

EEPROM

ProgrammedProgrammed

FTDI configuration

Not Programmed

Configuration Signals

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Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile , means (using a *.SOF file), means the configuration is lost after power off.

Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.

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FPGA Bank	Connector Designator	I/O Signal Count	Voltage Level	Notes
Bank 1A	J1	7	3.3V	AIN0...6
Bank 1B	J4	5	3.3V	JTAG interface
Bank 2	J1	4	3.3V	DIO2...5
Bank 5	J2	9	3.3V	DIO6...14
Bank 5	J1	2	3.3V	DIO0...1
Bank 8	J2	1	3.3V	RESET

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FPGA I/O Banks

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO Pin

Connected to

B2B

Notes

MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2

QSPI

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FPGA Bank	I/O Signal Count	Connected to	Notes
Bank 1A	7	1x14 Pin header, J1	AIN0...6
Bank 1A	1	Jumper, J3	AIN7
Bank 1B	5	1x6 Pin header, J4	JTAG_EN, TDI, TDO, TMS, TCK
Bank 2	1	12MHz Oscillator, U7	CLK12M
	4	1x14 Pin header, J1	D2...5
	4	A2D, U6	ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
	3	Amplifier, U12	AMP_A0, AMP_A1, AMP_A2
	1	A2D, U6	ADC_PWR_EN1
	1	100MHz Oscillator, U19	CLK_EN
Bank 3	22	SDRAM, U2	RAM_ADDR_CMD
Bank 3	1	A2D, U6	PDB_AMP
Bank 5	9	1x14 Pin header, J2	DIO6...14
	2	1x14 Pin header, J1	DIO0...1
	1	D12_R	DIO12
Bank 6	16	SDRAM, U2	DQ0...15
	2	SDRAM, U2	DQM0...1
	1	D11_R	DIO11
	1	A2D, U6	PDB_REF
Bank 8	8	User Red LEDs, D2...9	LED1...8
	6	SPI Flash, U5	F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn
	1	Red LED, D10	CONF_DONE
	6	FTDI JTAG/UART Adapter, U3	BDBUS0...5
	1	Push Button, S2	USER_BTN

Micro-

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USB Connector

The Micro-USB2 USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 FT2232H chip. The use of this feature requires that FTDI USB driver is drivers are installed on your host PC.

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Pins	Connected to	Note
VBUS	USB_VBUS
D+	FTDI FT2232H U3, DP pin
D-	FTDI FT2232H U3, DM pin

JTAG Interface

JTAG access to the TEI0023 FPGA through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

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JTAG Signal	Pin Header Connector	Note
TMS	J4-6
TDI	J4-5
TDO	J4-4
TCK	J4-3
JTAG_EN	J4-2	Pulled-up to 3.3V

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Chip/Interface	Designator	Notes
SDRAM	U2
FTDI FT2232H	U3	JTAG/UART/FIFO Adapter
SPI Flash	U5
EEPROM	U9
Oscillator	U7	12 MHz clock source
ADC	U12	Analog to Digital Converter
Push Buttons	S1...2
8x User LEDs	D2...9	Red LEDs

SDRAM

TEI0023 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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FTDI Chip U3 Pin	Signal Schematic Name	Connected to	Notes
ADBUS0	TCK	FPGA bank 1B, pin G2	JTAG interface
ADBUS1	TDI	FPGA bank 1B, pin F5
ADBUS2	TDO	FPGA bank 1B, pin F6
ADBUS3	TMS	FPGA bank 1B, pin G1
BDBUS0	BDBUS0	FPGA bank 8, pin A4	User configurable
BDBUS1	BDBUS1	FPGA bank 8, pin B4	User configurable
BDBUS2	BDBUS2	FPGA bank 8, pin B5	User configurable
BDBUS3	BDBUS3	FPGA bank 8, pin A6	User configurable
BDBUS4	BDBUS4	FPGA bank 8, pin B6	User configurable
BDBUS5	BDBUS5	FPGA bank 8, pin A7	User configurable
BDBUS6	BDBUS6	FPGA bank 6, pin C11	User configurable
BDBUS7	BDBUS7	FPGA bank 3, pin J7	User configurable
BCBUS0	BCBUS0	FPGA bank 5, pin J9	User configurable
BCBUS1	BCBUS1	FPGA bank 3, pin K5	User configurable
BCBUS2	BCBUS2	FPGA bank 3, pin L4	User configurable
BDBUS4BCBUS3BDBUS4	BCBUS3	FPGA bank 83, pin B6L5	User configurable
BDBUS5BCBUS4BDBUS5	BCBUS4	FPGA bank 83, pin A7N12	User configurable

SPI Flash

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

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Signal Schematic Name	Connected to	Notes
F_CS	FPGA bank 8, pin B3	Chip select
F_CLK	FPGA bank 8, pin A3	Clock
F_DI	FPGA bank 8, pin A2	Data in / out
nSTATUS	FPGA bank 8, pin C4	Data in / out, configuration dual-purpose pin of FPGA
DEVCLRN	FPGA bank 8, pin B9	Data in / out, configuration dual-purpose pin of FPGA
F_DO	FPGA bank 8, pin B2	Data in / out

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The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

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Schematic	Connected to	Notes
EECS	FTDI U3, Pin EECS
EECLK	FTDI U3, Pin EECLK
EEDATA	FTDI U3, Pin EEDATA

ADC

The TEI0023 The TEI0023-XX-XXA board is equipped with the Analog Devices ADAQ4003BBCZ 18-bit 2MSPS ADC.

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Power supply with minimum current capability of xx A 1A for system startup is recommended.

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FPGA	Typical Current
Intel MAX 10 10M08 FPGA SoC	TBD*

* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

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Power-On Sequence

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Bank	Schematic Name	Voltage
Bank 1A	VCCIO1A	3.3V
Bank 1B	VCCIO1B	3.3V
Bank 2	VCCIO2	3.3V
Bank 3	VCCIO3	3.3V
Bank 5	VCCIO5	3.3V
Bank 6	VCCIO6	3.3V
Bank 8	VCCIO8	3.3V

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Symbols	Description	Min	Max	Unit	Reference Document
VIN	Supply voltage	4.75	5.25	V
CH1-, CH1+	Analog input voltage on amplifier U12 pin 1, 10	-20	20	V	LTC6373 datasheet
T_STG	Storage Temperature	-2565	+85125	°C

Recommended Operating Conditions

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Symbols

Min

Max

Unit

Reference Document

VIN supply voltage (5.0V nominal)

4.75

5.25

V

Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)

-10

10

V

LTC6373 datasheet

T_OP

0

+7085

°C

W9864G6JT-6 datasheet

Part
W74M64FVSSIQ
DataSheet
W74M64FV

10M08SAU169C8G datasheet

Physical Dimensions

Module size: 25 mm × 86.5 mm. Please download the assembly diagram for exact numbers.

PCB thickness: 1.22 598 mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

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Trenz shop TE0728 overview page
English page	German page

Revision History

Hardware Revision History

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Date	Revision	Changes	Documentation Link
2020-02-03	Beta 101	Fill in TRM template	ADD LINKREV01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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Create DrawIO object here: Attention if you copy from other page, objects are only linked.
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Document Change History

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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Date

Revision

Contributor

Description

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change list

corrected link to Download area

2021-02-23

v.41

Antti Lukats

bugfix change history

2020-08-20

v.36

Antti Lukats

correction: Key features, overview, USB, SDRAM, SPI section

2020-02-04

v.33

ED, Kilian Jan

initial release

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Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

Trenz Electronic Documentation

Versions Compared

Old Version 15

New Version Current

Key

Key Features

Configuration Signals

FPGA I/O Banks

Micro-

USB Connector

JTAG Interface

SDRAM

SPI Flash

ADC

Power Distribution Dependencies

Power-On Sequence

Recommended Operating Conditions

Physical Dimensions

Revision History

Hardware Revision History

Document Change History

Disclaimer