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Table of Contents |
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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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Intel® MAX 10 Commercial FPGA [10M08SAU169C8G]
Package: UBGA-169
Speed Grade: C8 (Slowest)
Temperature: 0°C to 85°C (Commercial)
Package compatible device 10M0210M08...10M16 as assembly variant on request possible
SDRAM Memory up to 64 Mbyte, 166MHz32 Mbyte (8Mbyte default)
USB 2.0 Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mbit Quad SPI Flash - Not on all variants
(FT2232H)
- 4 Kbit EEPROM Memory for FTDI configuration data
8x User LED
- Micro USB Receptacle (communication and power)
- SPI Flash - NOT INSTALLED (only special option)
- 8x User LED'sMicro USB2 Receptacle 90
- 18 Bit 2 MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO - Arduino MKR compatible
Power Supply: 5V
Dimension: 86.5mm x 25mm
- Fully-Differential Programmable-Gain Instrumentation Amplifier
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SMA Connector, J5...6
Amplifier, U12
Series Voltage Reference, U8
Analog to Digital Converter, U6
Voltage Regulator, U4 - U10 - U13 - U16
Switching Voltage Regulator, U11
SDRAM Memory, U2
- Intel® MAX 10 FPGA, U1
SPI Flash Memory, U5 (not populated)
Oscillator, U7 - U19
FTDI USB2 USB to JTAG/UART FIFO Adapter, U3
User LEDs, D2...9
FTDI Configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-On LED (Green), D1
Push Button, S1...2
Micro USB Connector, J9
1x14 Pin Header, J2 (Not assembled)
1x6 Pin Header, J4 (Not assembled)
1x4 Pin Header, J3 (Not assembled)
1x14 Pin Header, J1 (Not assembled)
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Notes : Only components like EEPROM, QSPI SPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | N/A | Not Programmedpopulated | | EEPROM | ProgrammedProgrammed | FTDI configuration | SDRAM | Not Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.
Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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| anchor | Table_OBP_IOs |
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| title | FPGA I/O Banks |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | I/O Signal Count | Connected to | Notes |
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| Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 | | 1 | Jumper, J3 | AIN7 | | Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | Bank 2
| 1 | 12MHz Oscillator, U7 | CLK12M | | 4 | 1x14 Pin header, J1 | D2...5 | | 4 | A2D, U6 | ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | | 3 | Amplifier, U12 | AMP_A0, AMP_A1, AMP_A2 | | 1 | A2D, U6 | ADC_PWR_EN1 | | 1 | 100MHz Oscillator, U19 | CLK_EN | | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | | 1 | A2D, U6 | PDB_AMP | | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | | 2 | 1x14 Pin header, J1 | DIO0...1 | | 1 | D12_R | DIO12 | | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | | 2 | SDRAM, U2 | DQM0...1 | | 1 | D11_R | DIO11 | | 1 | A2D, U6 | PDB_REF | Bank 8
| 8 | User Red LEDs, D2...9 | LED1...8 | | 6 | SPI Flash, U5 | F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn | | 1 | Red LED, D10 | CONF_DONE | | 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | | 1 | Push Button, S2 | USER_BTN |
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Micro-
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USB Connector
The Micro-USB2 USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 FT2232H chip. The use of this feature requires that FTDI USB driver is drivers are installed on your host PC.
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| anchor | Table_OBP_USB |
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| title | Micro USB-2 connector pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pins | Connected to | Note |
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| VBUS | USB_VBUS |
| | D+ | FTDI FT2232H U3, DP pin |
| | D- | FTDI FT2232H U3, DM pin |
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JTAG Interface
JTAG access to the TEI0023 FPGA through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | Pin Header Connector | Note |
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| TMS | J4-6 |
| | TDI | J4-5 |
| | TDO | J4-4 |
| | TCK | J4-3 |
| | JTAG_EN | J4-2 | Pulled-up to 3.3V |
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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SDRAM
TEI0023 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency..
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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| ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | | ADBUS1 | TDI | FPGA bank 1B, pin F5 | | ADBUS2 | TDO | FPGA bank 1B, pin F6 | | ADBUS3 | TMS | FPGA bank 1B, pin G1 | | BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | User configurable | | BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | User configurable | | BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | User configurable | | BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | User configurable | | BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | User configurable | | BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | User configurable | | BDBUS6 | BDBUS6 | FPGA bank 6, pin C11 | User configurable | | BDBUS7 | BDBUS7 | FPGA bank 3, pin J7 | User configurable | | BCBUS0 | BCBUS0 | FPGA bank 5, pin J9 | User configurable | | BCBUS1 | BCBUS1 | FPGA bank 3, pin K5 | User configurable | | BCBUS2 | BCBUS2 | FPGA bank 3, pin L4 | User configurable | | BCBUS3 | BCBUS3 | FPGA bank 3, pin L5 | User configurable | | BCBUS4 | BCBUS4 | FPGA bank 3, pin N12 | User configurable |
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SPI Flash
| BCBUS3 | FPGA bank 3, pin L5 | User configurable | | BCBUS4 | BCBUS4 | FPGA bank 3, pin N12 | User configurable |
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SPI Flash
Optional SPI flash device maybe assembled in custom variants, normally it is not populatedOn-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
| Scroll Title |
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| anchor | Table_OBP_QSPI |
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| title | Quad SPI Flash memory interface |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signal Schematic Name | Connected to | Notes |
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| F_CS | FPGA bank 8, pin B3 | Chip select | | F_CLK | FPGA bank 8, pin A3 | Clock | | F_DI | FPGA bank 8, pin A2 | Data in / out | | nSTATUS | FPGA bank 8, pin C4 | Data in / out, configuration dual-purpose pin of FPGA | | DEVCLRN | FPGA bank 8, pin B9 | Data in / out, configuration dual-purpose pin of FPGA | | F_DO | FPGA bank 8, pin B2 | Data in / out |
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The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Connected to | Notes |
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EECS | FTDI U3, Pin EECS |
| | EECLK | FTDI U3, Pin EECLK |
| | EEDATA | FTDI U3, Pin EEDATA |
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ADC
The TEI0023-XX-XXA board is equipped with the Analog Devices ADAQ4003BBCZ 18-bit 2MSPS ADC.
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| Scroll Title |
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | Typical Current |
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| Intel MAX 10 10M08 FPGA SoC | TBD* |
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* TBD - To Be Determined
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
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| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | Connector J2 Pin | Connector J9 Pin | Direction | Notes |
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| VIN | J2-13 | - | Input | 5 V - Pin Header | | 3.3V | J2-12 | - | Output |
| | 5V | J2-14 | - | Output |
| USB_VBUS | - | J9-1 | Input | 5 V - USB Connector |
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Intel MAX 10 SoC bank voltagesMAX10 Bank Voltages. |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic Name | | Notes |
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| Bank 1A | VCCIO1A | 3.3V |
| | Bank 1B | VCCIO1B | 3.3V |
| | Bank 2 | VCCIO2 | 3.3V |
| | Bank 3 | VCCIO3 | 3.3V |
| | Bank 5 | VCCIO5 | 3.3V |
| | Bank 6 | VCCIO6 | 3.3V |
| | Bank 8 | VCCIO8 | 3.3V |
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Technical Specifications
Absolute Maximum Ratings
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| Scroll Title |
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| anchor | Figure_RV_HRN |
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| title | Board hardware revision number. |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramName | TEI0023_Revision-number |
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| simpleViewer | false |
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| width | 200 |
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| diagramWidth | 642 |
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| revision | 2 |
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
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| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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change list | | | v.41 | Antti Lukats | | | 2020-08-20 | v.36 | Antti Lukats | - correction: Key features, overview, USB, SDRAM, SPI section
| | 2020-02-04 | v.33 | ED, Kilian Jan | | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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Disclaimer
| Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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