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Table of Contents |
Overview
The Trenz Electronic TEI0023 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to httpsto http://wiki.trenz-electronic.de/display/PD/TEI0023+Resourcesorg/tei0023-info for the current online version of this manual and other available documentation.
Key Features
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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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Intel® MAX 10 Commercial FPGA [10M08SAU169C8G]
Package: UBGA-169
Speed Grade: C8 (Slowest)
Temperature: 0°C to 85°C (Commercial)
Package compatible device 10M0210M08...10M16 as assembly variant on request possible
SDRAM Memory up to 64Mb, 166MHz32 Mbyte (8Mbyte default)
USB 2.0 Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mb Quad SPI Flash
4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
(FT2232H)
- 4 Kbit EEPROM Memory for FTDI configuration data
- Micro USB Receptacle (communication and power)
- SPI Flash - NOT INSTALLED (only special option)
- 8x User LED's
- 18 Bit 2 MSPS 18 Bit 2 MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO - Arduino MKR compatible
Power Supply: 5V
Dimension: 86.5mm x 25mm
- Fully-Differential Programmable-Gain Instrumentation Amplifier
Block Diagram
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
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| title | TExxxx TE0023 main components |
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SMA Connector, J5...6
Amplifier, U12
Series Voltage Reference, U8
Analog to Digital Converter, U6
Voltage Regulator, U4 - U10 - U13 - U16
Switching Voltage Regulator, U11
SDRAM Memory, U2
- Intel® MAX 10 FPGA, U1
SPI Flash Memory, U5 (not populated)
Oscillator, U7 - U19
FTDI USB2 USB to JTAG/UART adapterFIFO Adapter, U3
User LEDs, D2...9
FTDI configuration Configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-on On LED (Green), D1
Push buttonButton, S1...2
Micro USB Connector, J9
1x14 pin headerPin Header, J2 (Not assembled)
1x6 pin headerPin Header, J4 (Not assembled)
1x4 Pin Header, J3 (Not assembled)
1x14 pin headerPin Header, J1 (Not assembled)
Initial Delivery State
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Notes : Only components like EEPROM, QSPI SPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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Storage device name | Content | Notes |
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Quad SPI Flash | N/A | Not Programmedpopulated | | EEPROM | ProgrammedProgrammed | FTDI configuration | SDRAM | Not Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.
Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| orientation | portraitSignal | Push Button | Pin Header | Note |
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RESET | S1 | J2 | Connected to nCONFIG |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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style | widths | | sortByColumn | 1 |
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Signal | B2B | I/O | Note |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
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I/Os on Pin Headers and Connectors
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| anchor | Table_SIP_B2BGIOs |
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| title | General PL I/O Os to B2B Pin Headers and connectors information |
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B2B | Connector Designator | I/O Signal Count | Voltage Level | Notes |
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JTAG access to the TExxxx SoM through B2B connector JMX.
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Bank 1A | J1 | 7 | 3.3V | AIN0...6 | | Bank 1B | J4 | 5 | 3.3V | JTAG interface | | Bank 2 | J1 | 4 | 3.3V | DIO2...5 | | Bank 5 | J2 | 9 | 3.3V | DIO6...14 | | J1 | 2 | 3.3V | DIO0...1 | | Bank 8 | J2 | 1 | 3.3V | RESET |
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FPGA I/O Banks
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JTAG Signal
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B2B Connector
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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| title | MIOs pinsFPGA I/O Banks |
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| FPGA Bank | I/O Signal Count |
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MIO PinB2B | |
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
| Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 | | Scroll Title |
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Test Point | Signal | Connected to | Notes |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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| anchor | Table_OBP |
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| title | On board peripherals |
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Quad SPI Flash Memory
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Notes :
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| 7 | 1x14 Pin header, J1 | AIN0...6 | | 1 | Jumper, J3 | AIN7 | | Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | Bank 2
| 1 | 12MHz Oscillator, U7 | CLK12M | | 4 | 1x14 Pin header, J1 | D2...5 | | 4 | A2D, U6 | ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | | 3 | Amplifier, U12 | AMP_A0, AMP_A1, AMP_A2 | | 1 | A2D, U6 | ADC_PWR_EN1 | | 1 | 100MHz Oscillator, U19 | CLK_EN | | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | | 1 | A2D, U6 | PDB_AMP | | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | | 2 | 1x14 Pin header, J1 | DIO0...1 | | 1 | D12_R | DIO12 | | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | | 2 | SDRAM, U2 | DQM0...1 | | 1 | D11_R | DIO11 | | 1 | A2D, U6 | PDB_REF | Bank 8
| 8 | User Red LEDs, D2...9 | LED1...8 | | 6 | SPI Flash, U5 | F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn | | 1 | Red LED, D10 | CONF_DONE | | 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | | 1 | Push Button, S2 | USER_BTN |
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Micro-USB Connector
The Micro-USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232H chip. The use of this feature requires that FTDI USB drivers are installed on your host PC.
| Scroll Title |
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| anchor | Table_OBP_SPIUSB |
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| title | Quad SPI interface MIOs and Micro USB-2 connector pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MIO Pin| Schematic | U?? Pin | Notes | |
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| Connected to | Note |
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| VBUS | USB_VBUS |
| | D+ | FTDI FT2232H U3, DP pin |
| | D- | FTDI FT2232H U3, DM pin |
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JTAG Interface
JTAG access to the TEI0023 FPGA through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.
| Scroll Title |
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| anchor | Table_OBPSIP_RTCJTG |
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| title | I2C interface MIOs and JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Scroll Title |
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| anchor | Table_OBP_I2C_RTC |
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| title | I2C Address for RTC |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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| TMS | J4-6 |
| | TDI | J4-5 |
| | TDO | J4-4 |
| | TCK | J4-3 |
| | JTAG_EN | J4-2 | Pulled-up to 3.3V |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: | Test Point | Signal | B2B | Notes |
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| 10 | PWR_PL_OK | J2-120 |
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| Scroll Title |
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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LEDs
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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| TP1 | +1.8 V | V_Lin, U13 ↔ A2D, U12 |
| | TP2 | VREF_OUT | V_Lin, U8 ↔ A2D, U6 |
| | TP6 | +14V_A | V_Lin, U10 ↔ Amplifier, U12 |
| | TP7 | -14V_A | V_Lin, U10 ↔ Amplifier, U12 |
| | TP8 | +14.5V | V_Switch, U11 / D11 ↔ L6 / V_Lin u10 |
| | TP9 | -14.5V | V_Switch, U11 / L12 ↔ L7 / V_Lin u10 |
| | TP10 | +5V5_A | u16 ↔ V_Lin, U8 / A2D, U12 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Page properties |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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SDRAM
TEI0023 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface.
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| Scroll Title |
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| anchor | Table_OBP_CANSDRAM |
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| title | CAN Tranciever interface MIOsSDRAM interface IOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Bank| SDRAM I/O Signals | Signal Schematic |
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U?? PinD-Tx | Driver Input | R-Rx | Reciever Output | |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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Programmable Clock Generator
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| Address inputs | A0 ... A13 | bank 3 | - | | Bank address inputs | BA0 / BA1 | bank 3 | - | | Data input/output | DQ0 ... DQ15 | bank 6 | - | | Data mask | DQM0 ... DQM1 | bank 6 | - | | Clock | CLK | bank 3 | - | | Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | | WE | bank 3 | Write Enable |
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FTDI FT2232H
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
|---|
| ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | | ADBUS1 | TDI | FPGA bank 1B, pin F5 | | ADBUS2 | TDO | FPGA bank 1B, pin F6 | | ADBUS3 | TMS | FPGA bank 1B, pin G1 | | BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | User configurable | | BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | User configurable | | BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | User configurable | | BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | User configurable | | BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | User configurable | | BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | User configurable | | BDBUS6 | BDBUS6 | FPGA bank 6, pin C11 | User configurable | | BDBUS7 | BDBUS7 | FPGA bank 3, pin J7 | User configurable | | BCBUS0 | BCBUS0 | FPGA bank 5, pin J9 | User configurable | | BCBUS1 | BCBUS1 | FPGA bank 3, pin K5 | User configurable | | BCBUS2 | BCBUS2 | FPGA bank 3, pin L4 | User configurable | | BCBUS3 | BCBUS3 | FPGA bank 3, pin L5 | User configurable | | BCBUS4 | BCBUS4 | FPGA bank 3, pin N12 | User configurable |
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SPI Flash
Optional SPI flash device maybe assembled in custom variants, normally it is not populated.
| Scroll Title |
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| anchor | Table_OBP_QSPI |
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| title | Quad SPI Flash memory interface |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signal Schematic Name | Connected to | Notes |
|---|
| F_CS | FPGA bank 8, pin B3 | Chip select | | F_CLK | FPGA bank 8, pin A3 | Clock | | F_DI | FPGA bank 8, pin A2 | Data in / out | | nSTATUS | FPGA bank 8, pin C4 | Data in / out, configuration dual-purpose pin of FPGA | | DEVCLRN | FPGA bank 8, pin B9 | Data in / out, configuration dual-purpose pin of FPGA | | F_DO | FPGA bank 8, pin B2 | Data in / out |
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EEPROM
The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Connected to | Notes |
|---|
EECS | FTDI U3, Pin EECS |
| | EECLK | FTDI U3, Pin EECLK |
| | EEDATA | FTDI U3, Pin EEDATA |
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ADC
The TEI0023-XX-XXA board is equipped with the Analog Devices ADAQ4003BBCZ 18-bit 2MSPS ADC.
| Scroll Title |
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| anchor | Table_OBP_A2D |
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| title | A2D converter interface and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pins | Connected to | Notes |
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IN+ | Instrumentation Amplifier U14, VOUT- |
| | IN- | Instrumentation Amplifier U14, VOUT+ |
| | SDI | FPGA, Bank 2, pin M2, ADC_SDI |
| | SDO | FPGA, Bank 2, pin M1, ADC_SDO |
| | SCK | FPGA, Bank 2, pin N3, ADC_SCK |
| | CNV | FPGA, Bank 2, pin N2, ADC_CNV |
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LEDs
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Connected to | Active Level | Note |
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| D2...9 | Red | LED1...8 | Active High | User LEDs | | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | | D1 | Green | 3.3V | Active High | After power on it will be on. |
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Push Bottuns
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| anchor | Table_OBP_PCLKLED |
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| title | Programmable Clock Generator Inputs and OutputsOn-board Push Buttons |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Connected to | Functionality | Note |
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| S1 | RESET | General reset |
| | S2 | USER_BTN | User push button | Connected to FPGA Bank 8. |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Clock Source | Schematic Name | Frequency | Note |
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| Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3. Connected to FPGA Bank 2, pin H6. |
U?? Pin
| Signal | Connected to | Direction | Note |
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IN0 | IN1 | IN2 | IN3 | XAXB | SCLK | SDA | OUT0 | OUT1 | OUT2 | OUT3 | OUT4 | OUT5 | OUT6 | OUT7 | OUT8/OUT9
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A 1A for system startup is recommended.
Power Consumption
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input PinFPGA | Typical CurrentCurrent |
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| Intel MAX 10 10M08 FPGA SoCVIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
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| Scroll Title |
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| anchor | Figure_PWR_PSPD |
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| title | Power SequencyDistribution |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Voltage Monitor Circuit
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| anchor | Figure_PWR_VMC |
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| title | Voltage Monitor Circuit |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
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| draw.io Diagram |
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| border | true |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 2 |
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| diagramName | TEI0023_PWR_PD |
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| simpleViewer | true |
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| width | |
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| links | auto |
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| tbstyle | top |
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| diagramWidth | 891 |
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| Scroll Only |
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 Image Added
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Power-On Sequence
There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.
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Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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B2B JM1 B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Connector J9 Pin | Direction | Notes |
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| VIN | J2-13 | - | Input | 5 V - Pin Header | | 3.3V | J2-12 | - | Output |
| | 5V | J2-14 | - | Output |
| USB_VBUS | - | J9-1 | Input | 5 V - USB Connector |
Notes
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Zynq Intel MAX 10 SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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...
...
use "include page" macro and link to the general B2B connector page of the module series,
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
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| Bank 1A | VCCIO1A | 3.3V |
| | Bank 1B | VCCIO1B | 3.3V |
| | Bank 2 | VCCIO2 | 3.3V |
| | Bank 3 | VCCIO3 | 3.3V |
| | Bank 5 | VCCIO5 | 3.3V |
| | Bank 6 | VCCIO6 | 3.3V |
| | Bank 8 | VCCIO8 | 3.3V |
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Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
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| anchor | Table_TS_AMR |
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| title | PS absolute maximum ratingsAbsolute Maximum Ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit |
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| Reference Document |
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VIN | Supply voltage | 4.75 | 5.25 | V |
| | CH1-, CH1+ | Analog input voltage on amplifier U12 pin 1, 10 | -20 | 20 |
VV | | LTC6373 datasheet | T_STG | Storage Temperature | -65 | +125 | °C |
V | V | V | V | V
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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ParameterUnits| V | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V |
| | Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+) | -10 | 10 | V | LTC6373 datasheet | T_OP | 0 | +85 | °C | 10M08SAU169C8G datasheet |
°C | See Xilinx ???? datasheet.
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Physical Dimensions
Module size:
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25 mm ×
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86.5 mm. Please download the assembly diagram for
...
exact numbers.
PCB thickness: ?? 1.598 mm.
| Page properties |
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 1 |
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| diagramName | TEI0023_Dimensions |
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| simpleViewer | true |
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| width | |
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| links | auto |
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| tbstyle | top |
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| diagramWidth | 642 |
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| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed Image Added |
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Currently Offered Variants
| Page properties |
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Set correct link to the shop page overview table of the product on English and German. Example for TE0728: ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
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| Scroll Title |
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| anchor | Table_VCP_SO |
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| title | Trenz Electronic Shop Overview |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Revision History
Hardware Revision History
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| Scroll Title |
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| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Changes | Documentation Link |
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| 2020-02-03 | 01 | Fill in TRM template | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
| Scroll Title |
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| anchor | Figure_RV_HRN |
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| title | Board hardware revision number. |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramName | TEI0023_Revision-number |
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| simpleViewer | false |
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| width | 200 |
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| diagramWidth | 642 |
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| revision | 2 |
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| Scroll Only |
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 Image Added
| Create DrawIO object here: Attention if you copy from other page, objects are only linked. | | Scroll Only |
|---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Document Change History
| Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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...
| Scroll Title |
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
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| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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| | | v.41 | Antti Lukats | | | 2020-08-20 | v.36 | Antti Lukats | - correction: Key features, overview, USB, SDRAM, SPI section
| | 2020-02-04 | v.33 | ED, Kilian Jan | | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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Disclaimer
| Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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