...
| Scroll Title |
|---|
| anchor | Figure_OV_BD |
|---|
| title | TExxxx block diagram |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramName | TEI0023_Block-diagram |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| diagramWidth | 642 |
|---|
| revision | 1 |
|---|
|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
|---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
...
| Scroll Title |
|---|
| anchor | Figure_OV_MC |
|---|
| title | TExxxx main components |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramName | TEI0023-Main_Components |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| diagramWidth | 642641 |
|---|
| revision | 34 |
|---|
|
|
| Scroll Only |
|---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
SMA Connector, J5...6
Amplifier, U12
Series Voltage Reference, U8
Analog to Digital Converter, U6
Voltage Regulator, U4 - U10 - U13 - U1U166
Switching Voltage Regulator, U11 - U4
SDRAM Memory, U2
- Intel® MAX 10, U1
SPI Flash Memory, U5
12.00 MHz MEMS oscillatorOscillator, U7 - U19
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
FTDI configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB Connector, J9
1x14 pin header, J2 (Not assembled)
1x6 pin header, J4 (Not assembled)
1x4 Header, J3 (Not assembled)
1x14 pin header, J1 (Not assembled)
...
| Scroll Title |
|---|
| anchor | Table_OV_IDS |
|---|
| title | Initial delivery state of programmable devices on the module |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Storage device name | Content | Notes |
|---|
Quad SPI Flash | Not Programmed |
| | EEPROM | Programmed | FTDI configuration | | SDRAM | Not ProgrammedSystem Controller CPLD |
|
|
|
|
|
|
|
|
|
|
|
Configuration Signals
| Page properties |
|---|
|
- Overview of Boot Mode, Reset, Enables.
|
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
| Scroll Title |
|---|
| anchor | Table_OV_BP |
|---|
| title | Boot process. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Signal | Push Button | Pin Header | Note |
|---|
RESET | S1 | J2 | Connected to nCONFIG |
MODE Signal State | Boot Mode
|
| Scroll Title |
|---|
| anchor | Table_OV_RST |
|---|
| title | Reset process. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
...