| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
U15 Pin
| Signal | Connected to | Direction | Note |
|---|
IN0 | IN0_P | Oscillator, U14 | Input |
| | IN1 | - | N.C | - |
| | IN2 | EXT_CLK_IN1 | B2B,J2 | Input |
| | IN3 | - | N.C |
|
| nRST | PLL_RSTN | FPGA Bank 65,U1 | Input |
| | SCL | MIO32_I2C1_SCL | Pin Header, J3 | Input |
| | SDA | MIO33_I2C1_SDA | Pin Header, J3 | Input |
| | OUT0...5 | CLKA...F | B2B,J2 | Output | 6x Differential Clocks | | OUT6 | B128_CLK0 | FPGA Bank 128,U1 | Output |
| | OUT7 | B129_CLK0 | FPGA Bank 129,U1 | Output |
| | OUT8 | CLK8 | FPGA Bank 65,U1 | Output |
| | OUT9 | PSMGT_100MHZ | FPGA Bank 505,U1 | Output |
| | OUT9A | CLK0A_100MHZ | B2B, J1 | Output |
|
|
