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anchor	Figure_OV_BD
title	TEF1002 block diagram

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draw.io Diagram

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Main Components

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anchor	Table_OV_CS
title	TEF1002 Control Signals

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Control signal	Switch / Button / LED / Pin	Signal Schematic Names	Connected to	Functionality	Notes
FMC_VADJ voltage selection	DIP switches S2-1, S2-2, S2-3	VID0 ... VID2	SC CPLD U11, pins K6, J5, K5	sets adjustable voltage for FMC connector	dependens on SC CPLD configuration
JTAG enable	DIP switch S2-4	JTAGEN	SC CPLD U11, pin E5	OFF: Module/FMC JTAG enabled, CPLD IOs ON: TEF1002 SC CPLD JTAG enabled,	- function in OFF position depends on SC CPLD configuration (JTAG on pin header J5 (for TEI0004)
Module JTAG select	DIP switch S2-5	M_JTAGEN	B2B JB1, pin 90	When S2-4 ON and S2-6 OFF: OFF: Module SOC JTAG enabled, ON: Module SC CPLD JTAG enabled -	(JTAG via micro USB J10)
FMC JTAG select	DIP switch S2-6	FMC_JTAG	SC CPLD U11,L3When S2-4 ON:	OFF: TEF1002 SC CPLD Module JTAG enabled ,(see S2-5) ON: FMC JTAG enabled	depends on SC CPLD configuration, only avialiable when 4x5 module installed (JTAG via micro USB J10)
Enable module power	DIP switch S2-7	CM0	SC CPLD U11, M3	Module power. Set ON to enable module power. (Power management depends on module. )	depends on SC CPLD configuration, only avialiable when 4x5 module installed
No sequenzing	DIP switch S2-8	CM1	SC CPLD U11, L2	Module Power management. Set ON to disable module CPLD power management. Power management depends on module and not all modules support extended power management with CPLD.	depends on SC CPLD configuration, only avialiable when 4x5 module installed
Boot Mode	DIP switch S3-1	CM2	SC CPLD U11, K2	Boot Mode for attached module (Default: OFF for primary SD boot and ON for primary QSPI boot. Depends also on module CPLD firmware).	depends on SC CPLD configuration, only avialiable when 4x5 module installed
FMC VADJ enable	DIP switch S3-2	USR0	SC CPLD U11, K1	ON: FMC VADJ enable also without installed FMC Card OFF: FMC_FADJ only enabled when FMC installed.	dependens on SC CPLD configuration, only avialiable when 4x5 module installed
Reset	Push button S1	BUTTON	SC CPLD U11, N6	Module Reset, Low active module reset. Pin force Power one reset on FPGA/SoC.	depends on SC CPLD configuration
2x User LED	Green LEDs D1, D2	LED1, LED2	SC CPLD U11, J5, K5	Depends on User configuration, curenntly both off, if not otherwise programmed.	depends on SC CPLD configuration
Board power indicator	Green LED D3	3V3IN	B2B JB1, pin 14, 16	ON: 3.3V on-board voltage available	-
Board status indicators	Green LED D4	-	SC CPLD U11, pin C2	ON: No failure. For other blinking status of this LED please refer to SC Firmware description.	dependens on SC CPLD configuration
Enable module power	SC CPLD U11, D11	EN1	B2B JB1, pin 27	Module power. (Power management depends on module. )	-In standard Firmware connected to CM0 (see above)
No sequenzing	SC CPLD U11, E13	NOSEQ	B2B JB1, pin 8	Power management depends on module and not all modules support extended power management with CPLD.	-In standard Firmware connected to CM1 (see above)
Boot Mode	SC CPLD U11, B11	MODE	B2B JB1, pin 31	Boot Mode for attached module. LOW for primary SD boot and HIGH for primary QSPI boot. (Depends also on module CPLD firmware).	-In standard Firmware connected to CM2 (see above)
Module Reset	SC CPLD U11, E12	RESIN	B2B JB2, pin 17	Module Reset-	In standard Firmware connected to BUTTON S1 (see above)

Signals, Interfaces and Pins

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anchor	Table_SIP_B2B
title	General overview of B2B connectors

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B2B Connector	Interfaces	I/O Signal Count	Notes
JB1	User IO	15 single ended or 7 differential	TEF1002 CPLD
		16 single ended or 8 differential	FFA
		16 single ended or 8 differential	FFB
	MIO/PJTAG/User IO	4	Pinheader J19
	CPLD IO	2	Module CPLD IO to Carrier CPLD
	SD IO	6	-
	UART	2	-
	GbE PHY_MDIO + PHY_COM	8 +1	-
	Module Control	5	NOSEQ,, EN1, PGOOD, MODE, M_JTAGEN
JB2JB3	User IO	12 single ended or 6 differential	LPC FMC
	MGTs (RX+TX)	4	PCIe x1, SFP+, LPC FMC, SATA
	MGTCLK	1 differential	-
	CLK	1 differential	-
	USB2	1 differnetial	OTG-D_P, OTG-D_N
	USB Control	3	OTG-ID
JB3JB2	User IO	56 single ended or 28 differential	LPC FMC
	CLK	2 differential	M2C
	JTAG	4	-

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title	FMC connector interface

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FMC Connector J2 Pins and Interfaces	I/O Signal Count	LVDSdiff.-pairs count	Connected to	VCCIO voltage	Notes
I/O	56	28	B2B JB2 connector	FMC_VADJ	pins usable as single ended I/O's or LVDS differential pairs
I/O	12	6	B2B JB3 connector	FMC_VADJ
Multi Gigabit Transceiver	-	2	B2B JB3 connector, pin 19, 21 and 20, 22	-	RX, TX
Gigabit Transceiver Clock	-	1	B2B JB3 connector, pin 31, 33	-
I²C (SDA, SCL)	2	-	SC CPLD U11, pin F9, J8	3V3IN	FMC I²C Geographical Address pins GA0 and GA1 set to GND.
JTAG	5	-	SC CPLD U11, pin N7, M8, F8, M7, N8	3V3IN	TDO, TMS, TCK, TDI, TRST
Clock Input	-	2	B2B JB3 connector	FMC_VADJ	2x reference clock inputs
Control Signals	2	-	SC CPLD U11, pin M5, E9	3V3IN	'PG_C2M', 'FMC_PRSNT'
Reference voltage (FMC_VREF)	-	-	-	-	Not Connected.

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title	SFP+ interface

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Connector J12 Pins and Interfaces	I/O Signal Count	LVDSdiff.-pairs count	Connected to	VCCIO voltage	Notes
Multi Gigabit Transceiver	-	2	B2B JB3 connector, pin 13, 15 and 14, 16	-	RX, TX
Control	6		SC CPLD U11	3V3IN	TX_FAULT, TX_DIS, M-DEF0, RS0, RS1, LOS
I²C (SDA, SCL)	2	-	SC CPLD U11, pin F9, J8	3V3IN	MUX via CPLD

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anchor	Table_SIP_PCIe
title	PCIe x1 card edge connector

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Connector J3 Pins and Interfaces	I/O Signal Count	LVDSdiff.-pairs count	Connected to	VCCIO voltage	Notes
Multi Gigabit Transceiver	-	2	B2B JB3 connector, pin 725, 9 27 and 826, 1028	-	RX, TX
Clock	-	1	B2B JB3 connector, pin 32, 34	-
JTAG	5	-	SC CPLD U11, M12, M13, L11, N12, G10	3V3IN	TDO, TMS, TCK, TDI, TRST

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title	SATA connector

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Connector J31 Pins and Interfaces	I/O Signal Count	LVDSdiff.-pairs count	Connected to	VCCIO voltage	Notes
Multi Gigabit Transceiver	-	2	B2B JB3 connector, pin 7, 9 and 8, 10	-	RX, TX

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High speed connectors FFA and FFB

There are two Firefly connector arrangements mechanical compatible to Firefly connectors, but with high speed LVDS signals.

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title	FMC connector interface

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Connector, Pins and Interfaces	I/O Signal Count	LVDSdiff.-pairs count	Connected to	VCCIO voltage	Notes
FFA, J11	-	8	B2B JB1 connector	-	-
FFA Control, J14	4	-	SC CPLD U11, pin C10, C9, E8, B9	3V3IN	MPRS, MSEL, INTL, RSTL
FFA I2C, J14	2	-	SC CPLD U11, pin E6, D6	3V3IN
FFB, J11	-	8	B2B JB1 connector	-	-
FFB Control, J14	4	-	SC CPLD U11, pin A11, B10, A10, B9	3V3IN	MPRS, MSEL, INTL, RSTL
FFB I2C, J14	2	-	SC CPLD U11, pin A9, D8	3V3IN

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The microUSB connector provides JTAG access to Module and FMC through the carriers USB to JTAG/UART/FIFO bridge. JTAG is routed for MUX and CPLD JTAG access to the CPLD. UART signals are connected to the module B2B connectors. For further description of the JTAG MUX see Dip dip switches or SC CPLD Firmware. For other non-standard functionalitiers compare on-board Peripherals connection and datasheet of FTDI FT2232H.

(CPLD JTAG access is via 2x5 pin header J5. See pin header description)

microUSB

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anchor	Table_SIP_USB
title	MicroUSB J16

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Connector J16, Pins and Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCIO voltage	Notes
DATA	-	1	B2B JB3 connector, pin 48, 50	-	-
Power, Control	3	-	B2B JB3 pin 52, 54, 56	-	OTG-ID, VBUS_V_EN, USB-VBUS

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title	micro SD-Card connector

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Connector J8 pin	Signal Schematic Name	Muxed to signal on Port Expander	Connected to	Notes
2, DAT3	SD-D3_LS	SD_D3	B2B JB1, pin 18	-
3, CMD	SD-CMD_LS	SD_CMD	B2B JB1, pin 26	-
5, CLK	SD-CCLK_LS	SD_CCLK	B2B JB1, pin 28	-
7, DAT0	SD-D0_LS	SD_D0	B2B JB1, pin 24	-
8, DAT1	SD-D1_LS	SD_D1	B2B JB1, pin 22	-
1, DAT2	SD-D2_LS	SD_D2	B2B JB1, pin 20	-
9, CARD Detectdetect	SD-CD	-	U11, pin M1	CPLD Firmware dependent, in default firmware not used

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The Intel/Altera MAX10 10M08SAU169C8G System Controller CPLD (U11) is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware. It generates output signals to control the system, the on-board peripherals and the interfaces. The JTAG and I²C between the on-board peripherals and the attached module are by-passed, forwarded and controlled by the System Controller CPLD. A main tasks of the System Controller CPLD is the monitoring of the power-on sequence and configuring the state of the attached module. For detailed information, refer to the firmware documentation of the SC CPLD. Table below lists the SC CPLD I/O signals and pins:

Not used

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anchor	Table_SIP_CPLD
title	SC CPLD pin mapping

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Signal name	SC CPLD Pin	Connected to	Function	Notes
ACBUS0	A4	FTDI U4, pin 22	GPIO's available to user	(FIFO or other FTDI functions when FTDI reprogrammed)
ACBUS1	B4	FTDI U4, pin 23
ACBUS2	A5	FTDI U4, pin 24
ACBUS3	B5	FTDI U4, pin 25
ACBUS4	A6	FTDI U4, pin 26
ACBUS5	B6	FTDI U4, pin 27
ACBUS6	A7	FTDI U4, pin 28
ACBUS7	A8	FTDI U4, pin 29
ADBUS4	A2	FTDI U4, pin 17
ADBUS5	B2	FTDI U4, pin 18
ADBUS6	A3	FTDI U4, pin 19
ADBUS7	B3	FTDI U4, pin 20
TCK	G2	J5, 1	CPLD JTAG signals from pin header	Other functions possible with non standard CPLD firmware.
TDI	F5	J5, 9
TDO	F6	J5, 3
TMS	G1	J5, 5
F_TCK	H3	FTDI U4, pin 12	Forwarded JTAG signals from FTDI chip.	(FIFO or other FTDI functions when FTDI reprogrammed)
F_TDI

F5

H2	FTDI U4, pin 13
F_TDO

F6

G4	FTDI U4, pin 14
F_TMS

G1

F4	FTDI U4, pin 15
M_TCK	H5	JB2, pin 100	4x5 Module JTAG	Bank with VCCIO is VREF_JTAG from Module
M_TDI	J2	JB2, pin 96
M_TDO	J1	JB2, pin 98
M_TMS	H6	JB2, pin 94
FMC_TCK	F8	J1, pin D29	FMC JTAG	TRST not used
FMC_TDI	M7	J1, pin D30
FMC_TDO	N7	J1, pin D31
FMC_TMS	M8	J1, pin D33
FMC_TRST	N8	J1, pin D34
PCIE_TCK	L11	J3, pin A5	PCIe JTAG	Currently not used
PCIE_TDI	N12	J3, pin A6
PCIE_TDO	M12	J3, pin A7
PCIE_TMS	M13	J3, pin A8
PCIE_TRST	G10	J3, pin B9
PCIE_PERST	F12	J3, pin A11	Indication that PCIe Bus is up (power, clocks)
EN_FMC	L4	U14, pin 9	Enable switched 3.3V FMC power	pulled down
EN_FMC_VADJ	K7	U1, pin 41	Enable IO power FMC_VADJ	pulled down
EN_PER	F13	Q4, pin 5	Enable perepherie power 3V3_PER	pulled down
FAN_FMC_EN	K8	Q1, pin 5	Enable FMC FAN	floating during configuration (no pull down)
FMC_PG_C2M	M5	J1, pin D1	Indicate that all FMC related powers are up	pulled up
FMC_PRSNT_M2C_L	E9	J1, pin H2	Indicate if FMC installed	Low when FMC present
FMC_SCL	J8	J1, pin C31	I²C 2-wire serial bus	MUX in CPLD
FMC_SDA	F9	J1, pin C30	I²C 2-wire serial bus	MUX in CPLD
PG_FMC_VADJ	J6	U1, pin 35	Indicate FMC VADJ power is up
FF_RSTL	B9	J13, pin 6 and J18, pin 6	Reset configuration	Both FF are resetted simultanously when pulled LOW
FFA_INTL	E8	J13, pin 5	Indicate interrrupt	LOW when fault condition, pulled up
FFA_MPRS	C10	J13, pin 3	Indicate FF Module installed	LOW when Module present, pulled up
FFA_MSEL	C9	J13, pin 4	Select attached FF Module	Pull low to use I²C
FFA_SCL	D6	J13, pin 8	I²C 2-wire serial bus	MUX in CPLD
FFA_SDA	E6	J13, pin 7	I²C 2-wire serial bus	MUX in CPLD
FFB_INTL	A10	J18, pin 5	Indicate interrrupt	LOW when fault condition, pulled up
FFB_MPRS	A11	J18, pin 3	Indicate FF Module installed	LOW when Module present, pulled up
FFB_MSEL	B10	J18, pin 4	Select attached FF Module	Pull low to use I²C
FFB_SCL	D8	J18, pin 8	I²C 2-wire serial bus	MUX in CPLD
FFB_SDA	A9	J18, pin 7	I²C 2-wire serial bus	MUX in CPLD
CPLD_IO_1	B12	JB1, pin 88	(M)IOs from 4x5 Module	(M)IOs used for ETH PHY LEDs
CPLD_IO_2	A12	JB1, pin 92	(M)IOs from 4x5 Module	(M)IOs used for ETH PHY LEDs
M10_RST	D1

TP22

J5, pin 6		Currently not used, functions possible with non standard CPLD firmware.
M10_RX			E4

TP24

J5, pin 8
M10_TX	E3

TP23

J5, pin 7
EN1	D11	JB1, pin 27	Enable on module power	Depends on module, on some similar to reset.
MODE	B11	JB1, pin 31	Boot Mode selection	For Zynq modules only. (LOW → SD, HIGH → primary QSPI)
NOSEQ	E13	JB1, pin 8	Disable module CPLD power management	Depends on module. On some modules no extended CPLD power management avaialble.
PGOOD	C11	JB1, pin 29	Power good signal	This is only for monitoring, do not use as powerenable! Pulled up.
RESIN	E12	JB2, pin 17	Module Reset	Aktive LOW
M3.3VOUT	M4	JB2, pin 9 and 11	Indicates module power is up	Used for perepherie power enable. Floating when no module installed (no pull down).
SFPA_LOS	M10	J12, pin 8	SFP signal loss	HIGH indicates signal loss
SFPA_M-DEF0	F10	J12, pin 6	SFP modul absent	HIGH when module physically absent
SFPA_RS0	N10	J12, pin 7	SFP rate select RX	LOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_RS1	M11	J12, pin 9	SFP rate select TX	LOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_SCL	L10	J12, pin 5	I²C 2-wire serial bus	MUX in CPLD
SFPA_SDA	N9	J12, pin 4	I²C 2-wire serial bus	MUX in CPLD
SFPA_TX_DIS	M9	J12, pin 3	SFP transmitter disable	HIGH disables transmitter
SFPA_TX_FAULT	G9	J12, pin 2	Indicates SFP laser fault	HIGH indicates fault
VID0_FMC_VADJ	E10	U1, pin 34	FMC_VADJ Voltage select	Chip internal pulled up
VID1_FMC_VADJ	J7	U1, pin 33
VID2_FMC_VADJ	L5	U1, pin 32
VID0	K6	S2-1	For FMC_VADJ Voltage select
VID1	N5	S2-2
VID2	N4	S2-3
JTAGEN	E5	S2-4
FMC_JTAG

L3

B1	S2-6	Enable FMC JTAG port
CM0	M3	S2-7	Dips for module control signals
CM1	L2	S2-8
CM2	K2	S3-1
USR0

K1

C1	S3-2	User button	Currently used for override FMC VADJ enable
USB_OC	D9	U12, pin 5	USB overcurrent detection
EN_5VSATA	E1	U15, pin 1	Enable SATA pin 7 power
OC_VSATA	F1	U15, pin 2	Overcurrent detection SATA pin 7 power
BUTTON	N6	S1	Reset button
SD-CD	M1	J8, pin 9	SD-Card card detect switch	Currently not used
LED1	J5	D1

user

User LED
User LED		LED2	K5	D2
-	C2	D4	Status LED	For further explanation see SC CPLD Firmware description
PHY_LED1	D12	J9	Phy LEDs
PHY_LED1R	C13	J9
PHY_LED2	B13	J9
PHY_LED2R	C12	J9
A_00_N	J10	JB1, pin 38	Module to CPLD communication	Currently "three wire" I²C and RGPIO, see SC CPLD Firmware description
A_00_P	K10	JB1, pin 36
A_01_N	L12	JB1, pin 35
A_01_P	K11	JB1, pin 37
A_02_N	J12	JB1, pin 41
A_02_P	K12	JB1, pin 39
A_03_N	H10	JB1, pin 44
A_03_P	J9	JB1, pin 42
A_04_N	H13	JB1, pin 47
A_04_P	J13	JB1, pin 45
A_05_N	H8	JB1, pin 57
A_05_P	H9	JB1, pin 55
A_06_N	G12	JB1, pin 49
A_06_P	G13	JB1, pin 51
A_07	L13	JB1, pin 34

Trenz Electronic Documentation

Versions Compared

Old Version 28

New Version 29

Key

Main Components

Signals, Interfaces and Pins

High speed connectors FFA and FFB

microUSB

FTDI FT2232H

Pin Header

On-board LEDs