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anchor	Table_OBP_I2C_EEPROM
title	I2C address for EEPROM

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueMIO PinI2C AddressDesignatorNotes

LEDs

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anchor	Table_OBP_LED
title	On-board LEDs

TP1 +1.8 V V_Lin, U13   ↔   A2D, U12 TP2 VREF_OUT V_Lin, U8   ↔   A2D, U6 TP6 +14V_A V_Lin, U10   ↔   Amplifier, U12 TP7 -14V_A V_Lin, U10   ↔   Amplifier, U12 TP8 +14.5V V_Switch, U11 / D11   ↔   L6 / V_Lin u10 TP9 -14.5V V_Switch, U11 / L12   ↔   L7 / V_Lin u10 TP10 +5V5_A u16   ↔   V_Lin, U8 / A2D, U12

On-board Peripherals

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hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor Table_OBP title On board peripherals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Chip/Interface Designator Notes TRM TEI0023 U2 FTDI FT2232H U3 JTAG/UART Adapter SPI Flash U5 TRM TEI0023 U9 Oscillator U7 12 MHz clock source TRM TEI0023 U12 Analog to Digital Converter Push Buttons S1...2 8x User LEDs D2...9 Red LEDs

SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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hidden true id Comments
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchor Table_OBP_SDRAM title SDRAM interface IOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true SDRAM I/O Signals Signal Schematic Name Connected to Notes Address inputs A0 ... A13 bank 3 - Bank address inputs BA0 / BA1 bank 3 - Data input/output DQ0 ... DQ15 bank 6 - Data mask DQM0 ... DQM1 bank 6 - Clock CLK bank 3 - Control Signals CS bank 3 Chip select CKE bank 3 Clock enable RAS bank 3 Row Address Strobe CAS bank 3 Column Address Strobe WE bank 3 Write Enable

FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip. FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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anchor Table_OBP_FTDI title FTDI chip interfaces and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FTDI Chip U3 Pin Signal Schematic Name Connected to Notes ADBUS0 TCK FPGA bank 1B, pin G2 JTAG interface ADBUS1 TDI FPGA bank 1B, pin F5 ADBUS2 TDO FPGA bank 1B, pin F6 ADBUS3 TMS FPGA bank 1B, pin G1 BDBUS0 BDBUS0 FPGA bank 8, pin A4 User configurable BDBUS1 BDBUS1 FPGA bank 8, pin B4 User configurable BDBUS2 BDBUS2 FPGA bank 8, pin B5 User configurable BDBUS3 BDBUS3 FPGA bank 8, pin A6 User configurable BDBUS4 BDBUS4 FPGA bank 8, pin B6 User configurable BDBUS5 BDBUS5 FPGA bank 8, pin A7 User configurable

SPI Flash

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

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anchor Table_OBP_QSPI title Quad SPI Flash memory interface
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal Schematic Name Connected to Notes F_CS FPGA bank 8, pin B3 Chip select F_CLK FPGA bank 8, pin A3 Clock F_DI FPGA bank 8, pin A2 Data in / out nSTATUS FPGA bank 8, pin C4 Data in / out, configuration dual-purpose pin of FPGA DEVCLRN FPGA bank 8, pin B9 Data in / out, configuration dual-purpose pin of FPGA F_DO FPGA bank 8, pin B2 Data in / out

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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anchor Table_OBP_EEP title I2C EEPROM interface MIOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Schematic Connected to Notes EECS FTDI U3, Pin EECS EECLK FTDI U3, Pin EECLK EEDATA FTDI U3, Pin EEDATA

ADC

The TEI0023 board is equipped with the Analog Devices ADAQ4003BBCZ 18-bit 2MSPS ADC.

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anchor Table_OBP_A2D title A2D converter interface and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Pins Connected to Notes IN+ Instrumentation Amplifier U14, VOUT- IN- Instrumentation Amplifier U14, VOUT+ SDI FPGA, Bank 2, pin M2, ADC_SDI SDO FPGA, Bank 2, pin M1,  ADC_SDO SCK FPGA, Bank 2, pin N3,  ADC_SCK CNV FPGA, Bank 2, pin N2, ADC_CNV

LEDs

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DDR3 SDRAM

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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

• Part number: 
• Supply voltage:
• Speed: 
• NOR Flash
• Temperature: 

Ethernet

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anchor Table_OBP_ETHLED title Ethernet PHY to Zynq SoC connectionsOn-board LEDs
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U?? Pin	Signal Name	Connected to	Signal Description	Note

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style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Color Connected to Active Level Note D2...9 Red LED1...8 Active High User LEDs D10 Red CONF_DONE Active Low Configuration DONE LED D1 Green 3.3V  Active High After power on it will be on.

Push Bottuns

Reciever Output

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anchor Table_OBP_CANLED title CAN Tranciever interface MIOsOn-board Push Buttons
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Connected to Functionality Note S1 RESET General reset S2 USER_BTN User push button Connected to FPGA Bank 8.
Bank	Schematic	U?? Pin	Notes
D-Tx	Driver Input	R-Rx