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The Trenz Electronic TE0823 (3PIU1FA /3PIU1FL) is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ ZU3CGMPSoC, 1 GByte LPDDR4 SDRAM, 128 MByte , 8 GB eMMC chip, 2x 64 MB Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.
The highly integrated modules are All this on a tiny footprint, smaller than a credit card , at the most competitive price. Modules in and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are fully completely mechanically and largely electrically compatible among with each other.
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Refer to http://trenz.org/te0823-info for the current online version of this manual and other available documentation.
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC/FPGA
- Package: SFVC784, SFRC784
- Device: ZU2 ...ZU5, *
- Engine: EG, CG, EV, *
- Speed: -1, -1L, -2, -2L, 3, *, **
- Temperature: I, E, *, **
- Xilinx Zynq UltraScale+ XCZU3CG-L1SFVC784I
- Application Processor: Dual-core ARM Cortex-A53 MPCore
- Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
- Package: SFVC784
- Device: ZU3
- Engine: CG
- Speed: -1LI (also non-low power assembly options possible)
- Temperature range: industrial
- RAM/Storage
- Low power DDR4 on PS with 32 bit data width
- 2x DDR4 SDRAM,
- Data Width: 32 Bit
- Size: 16 Gb, *
- Speed: 3733 Mbps, ***
- 2x 128 MByte QSPI boot Flash in dual parallel mode
- Data Width: 8 Bit
- Size: 512 Mb Gb, *
- 1x 8 GByte e.MMC memory with 8 bit data widthMemory
- Data Width: 8 Bit
- Size: 32 Gb, *
- MAC address serial EEPROM with EUI-48 node identity
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY
- MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 4x LEDS
- Interface
- 1x GB/s serial GMII interface
- 1x Hi-speed USB2 ULPI transceiver with full OTG support
Interface- 132 x HP PL 154 x High Performance (HP) und 96 x High Density (HD) I/Os (3 banks)
- ETH
- USB
- 78 x PS MIOs
- 4 x serial PS GTR transceivers4 GTR (for USB3, SATA, PCIe, DP)
Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:14 x PS MIOs- MIO for UART
- thereof 6 MIO for SD card interface (default configuration)
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V main input
3.3V controller input- Variable bank I/O power input
- All power supplies regulators on board
- Dimension
- Note
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
- Rugged for shock and high vibration
Notes- Rugged for shock and high vibration
- Evenly spread supply pins for good signal integrity
- Plug-on module with 2 x 100 pin and 1 x 60 pin Razor Beam High-Speed hermaphroditic Terminal/Socket Strips (low profile, 2,5 mm)
BlockDiagram
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Main Components
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- Xilinx Zynq UltraScale+ XCZU3EG, U1
- Red LED (ERR_OUT), D3
- Green User LED, D2
- Green LED (ERR_STATUS), D4
- Red LED (DONE), D1
- 10/100/1000 Mbps energy efficient ethernet transceiver, U8
- 8Gb DDR4, U2-U3
- 512 Mbit QSPI flash memory, U7-U17
- B2B connector Samtec Razor Beam, JM1
- B2B connector Samtec Razor Beam, JM3
- Programmable clock generator, U10
- USB2.0 Transceiver, U18
- B2B connector Samtec Razor Beam, JM3B2B connector Samtec Razor Beam, JM2
- 8 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
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title | Boot process. |
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MODE Signal State | Boot Mode |
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LowHigh | QSPI* | HighLow | SD Card* |
*changable also with other CPLD Firmware:TE0823 CPLD |
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Signal | B2B | I/O | Note |
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ENRESIN | JM1JM2-2818 | InputCPLD Enable Pin |
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Signals, Interfaces and Pins
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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24 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 25 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 26 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 44 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 65 | HP | JM2 | 18x I/O, 9x LVDS Pairs | Variable | Max voltage 1.8V | 65 | HP | JM3 | 16x I/O, 8x LVDS Pairs | Variable | Max voltage 1.8V | 505 | GTR | JM3 | 16x I/O, 8x LVDS Pairs | - | 4x lanes | 505 | GTR CLK | JM3 | 1x Diff Clock | - |
| 501 | MIO | JM1 | 15 I/O | 3.3V |
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Test Point | Signal | Connected to | Notes |
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1 |
Test Point | Signal | Connected to | Notes |
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1 | I2C_SCL | EEPROM, U25 | 2 | I2C_SDA | EEPROM, U25 | 3 | SRST_B | FPGA Bank 503 | PSCONFIG | 4 | PS_CLK | FPGA Bank 503 | PSCONFIG | 5 | PROG_B | FPGA Bank 503 | PSCONFIG | 6 | INIT_B | FPGA Bank 503 | PSCONFIG | 7 | DONE | Red LED, D1 | 8Voltage 9DDR2V5B | FPGA Bank 503, U1H | PSCONFIG | 3 |
Voltage Regulator, U4 | 10Voltage Voltage 11 | DDR_1V2 | 12Voltage U313U13 |
| 6 | - | - |
| 7 | PS_FP0V85 | Regulator, U26 |
| 8 | PS_LP0V85 | Voltage Regulator, | U2614 Translator15
| 10 | PS_PLL | Voltage Regulator, U23 |
| 11 | PL_VCCINT | Voltage Regulator, | U23VCCINT U5
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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The TE0821 is equipped with dual Flash Memory, U7, U17. Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT flash memory chips are provided for FPGA configuration file and data storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
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MIO Pin | Schematic | U?? Pin | | Notes | QSPI, U7 | QSPI, U17Notes |
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nCS | MIO5 | MIO7 |
| CLK | MIO0 | MIO12 |
| DI/IO0 | MIO4 | MIO8 |
| DO/IO1 | MIO1 | MIO9 |
| nHOLD/IO3 | MIO3 | MIO11 |
| WP/IO2 | MIO2 | MIO10 |
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EEPROM
There is a 2Kb EEPROM provided on the module TE0821.
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title | I2C EEPROM interface MIOs and pins |
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MIO Pin | Schematic | U?? Pin | Notes |
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MIO39 | I2C_SDA | SDA |
| MIO38 | I2C_SCL | SCL |
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MIO Pin | I2C Address | Designator | Notes |
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MIO38-MIO39 | 0x50 | U25 |
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LEDs
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Designator | Color | Connected to | Active Level | Note |
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D1 | Red | DONE | Low |
| D2 | Green | USR_LED | High |
| D3 | Red | ERR_OUT | High |
| D4 | Green | ERR_STATUS | High |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The
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TE0823 SoM has
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a 1 GB volatile LPDDR4 SDRAM IC for storing user application code and data.
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- IS43LQ32256A
- Supply voltage: 1.7V ~ 1.
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- 3200 Mbps
- Temperature: -40 ~ 95 °C
Gigabyte Ethernet
On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U11).
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title | Osillators |
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Designator | Description | Frequency | Note |
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U11 | MEMS Oscillator | 25 MHz |
| U14 | MEMS Oscillator | 52 MHz |
| U32 | MEMS Oscillator | 80 MHz |
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USB2.0 Transceiver
Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).
eMMC Flash Memory
eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.
Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.
A 25.00 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.
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title | Programmable Clock Generator Inputs and Outputs |
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U25 Pin
| Signal | Connected to | Direction | Note |
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IN0..1 | CLK_IN | JM3 | IN |
| IN2 | CLK_25M | Oscillator, U11 | IN |
| SCL | I2C_SCL | EEPROM,U25 | INOUT |
| SDA | I2C_SDA | EEPROM,U25 | INOUT |
| CLK0 | CLK0 | JM3 | OUT |
| CLK1 | B505_CLK3 | FPGA Bank 505 | IN |
| CLK2 | B505_CLK1 | FPGA Bank 505 | IN |
| CLK3 | CLK3_N |
| IN |
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Power supply with minimum current capability of xx 2.5 A for system startup is recommended.
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Power-On Sequence
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Power Rails
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board |
| 3.3V | - | 10, 12 | Output | Internal 3.3V voltage level |
| 3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board |
| 1.8V | 39 | - | Output | Internal 1.8V voltage level |
| JTAG VREF | - | 91 | Output | JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" |
| VCCO_64 | - | 7, 9 | Input | High performance I/O bank voltage |
| VCCO_65 | - | 5 | Input | High performance I/O bank voltage |
| VCCO_66 | 9, 11 | - | Input | High performance I/O bank voltage |
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B ConnectorsPD: |
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| 6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| PD:4 x 5 SoM LSHM B2B ConnectorsPD: |
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| 4 x 5 SoM LSHM B2B Connectors |
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title | Recommended operating conditions. |
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Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.3 | 6 | V | See TPS82085S datasheet | 3.3VIN supply voltage | 3.3 | 3.465 | V | See LCMXO2-256HC, Xilinx DS925 datasheet | PS I/O supply voltage, VCCO_PSIO | 1.710 | 3.465 | V | Xilinx document DS925 | PS I/O input voltage | –0.20 | VCCO_PSIO + 0.20 | V | Xilinx document DS925 | HP I/O banks supply voltage, VCCO | 0.950 | 1.9 | V | Xilinx document DS925 | HP I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx document DS925 | Voltage on SC CPLD pins | -0.3 | 3.6 | V | Lattice Semiconductor MachXO2 datasheet | Operating Temperature Range | 0 | 85 | °C | Xilinx document DS925, extended grade Zynq temperarure range |
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Date | Revision | Changes | Documentation Link |
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2018-09-25 | REV01 | Initial Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
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| | 2021-08-23 | v.42 | Pedram Babakhani | | 2020-11-02 | v.40 | Pedram Babakhani | | -- | all | Page info |
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