Versions Compared

Old Version 13

changes.mady.by.user Pedram Babakhani

Saved on

compared with

New Version Current

changes.mady.by.user John Hartfiel

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

The Trenz Electronic TE0823 (3PIU1FA /3PIU1FL)  is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ ZU3CGMPSoC, 1 GByte LPDDR4 SDRAM, 128 MByte , 8 GB eMMC chip, 2x 64 MB Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections..  The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.

The highly integrated modules are All this on a tiny footprint, smaller than a credit card , at the most competitive price. Modules in and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are fully completely mechanically and largely electrically compatible among with each other.

All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Refer to http://trenz.org/te0823-info for the current online version of this manual and other available documentation.

...

Page properties
hiddentrue
idComments

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • SoC/FPGA
    • Package: SFVC784, SFRC784
    • Device: ZU2 ...ZU5, *
    • Engine:  EG, CG, EV, *
    • Speed: -1, -1L, -2, -2L, 3, *, **
    • Temperature: I, E, *, **
    • Xilinx Zynq UltraScale+ XCZU3CG-L1SFVC784I
      • Application Processor: Dual-core ARM Cortex-A53 MPCore
      • Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
    • Package: SFVC784
    • Device: ZU3
    • Engine: CG
    • Speed: -1LI (also non-low power assembly options possible)
    • Temperature range: industrial
  • RAM/Storage
    • Low power DDR4 on PS with 32 bit data width
    • 2x  DDR4 SDRAM,
      • Data Width: 32 Bit
      • Size: 16 Gb, *
      • Speed: 3733 Mbps, ***
    • 2x 128 MByte QSPI boot Flash in dual parallel mode
      • Data Width: 8 Bit
      • Size: 512 Mb Gb, *
    • 1x 8 GByte e.MMC memory with 8 bit data widthMemory
      • Data Width: 8 Bit
      • Size: 32 Gb, *
    • MAC address serial EEPROM with EUI-48 node identity
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY
    • MachXO2 CPLD
    • Programmable Clock Generator
    • Hi-speed USB2 ULPI Transceiver
    • 4x LEDS
  • Interface
    • 1x GB/s serial GMII interface
    • 1x Hi-speed USB2 ULPI transceiver with full OTG support
    Interface
    • 132 x HP PL 154 x High Performance (HP) und 96 x High Density (HD) I/Os (3 banks)
    • ETH
    • USB
    • 78 x PS MIOs
    • 4 x serial PS GTR transceivers
        4 GTR (for USB3, SATA, PCIe, DP)
        Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:
        • PCI Express interface version 2.1 compliant
        • SATA 3.1 specification compliant interface

        • DisplayPort source-only interface with video resolution up to 4k x 2k

        • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate1 GB/s serial GMII interface
      • 14 x PS MIOs
        • MIO for UART
        • thereof 6 MIO for SD card interface (default configuration)
        • MIO for PJTAG
      • JTAG
      • Ctrl
    • Power
      • 3.3V-5V main input
      • 3.3V controller input
      • Variable bank I/O power input
      • All power supplies regulators on board
    • Dimension
      • 4 x 5 cm
      • 40 x 50 mm
    • Note
      • * depends on assembly version
      • ** also non low power assembly options possible
      • *** depends on used U+ Zynq and DDR4 combination
      • Rugged for shock and high vibration
      Notes
      • Rugged for shock and high vibration
      • Evenly spread supply pins for good signal integrity
      • Plug-on module with 2 x 100 pin and 1 x 60 pin Razor Beam High-Speed hermaphroditic Terminal/Socket Strips (low profile, 2,5 mm)

    BlockDiagram

    Page properties
    hiddentrue
    idComments

    add drawIO object here.


    Note

    For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


    ...

    Scroll Title
    anchorFigure_OV_BD
    titleTE0823 block diagram


    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue
    draw.io Diagram
    borderfalse
    diagramNameTE0823_OV_BD
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramDisplayName
    lboxtrue
    diagramWidth641
    revision916


    Scroll Only


    Main Components

    ...

    1. Xilinx Zynq UltraScale+ XCZU3EG, U1
    2. Red LED (ERR_OUT), D3
    3. Green User LED, D2
    4. Green LED (ERR_STATUS), D4
    5. Red LED (DONE), D1
    6. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
    7. 8Gb DDR4, U2-U3
    8. 512 Mbit QSPI flash memory, U7-U17
    9. B2B connector Samtec Razor Beam, JM1
    10. B2B connector Samtec Razor Beam, JM3
    11. Programmable clock generator, U10
    12. USB2.0 Transceiver,  U18B2B connector Samtec Razor Beam, JM3U18
    13. B2B connector Samtec Razor Beam, JM2
    14. 8 GByte eMMC memory, U6
    15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

    ...

    Scroll Title
    anchorTable_OV_BP
    titleBoot process.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    MODE Signal State

    		Boot Mode
    LowHigh

    QSPI*

    HighLowSD Card*

    *changable also with other CPLD Firmware:TE0823 CPLD



    Scroll Title
    anchorTable_OV_RST
    titleReset process.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Signal

    		B2BI/ONote

    ENRESIN

    		JM1JM2-2818InputCPLD Enable Pin


    Signals, Interfaces and Pins

    ...

    8
    Scroll Title
    anchorTable_SIP_TPs
    titleTest Points Information

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    stylewidths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Test PointSignalConnected toNotes
    1
    Test PointSignalConnected toNotes
    1I2C_SCLEEPROM, U252I2C_SDAEEPROM, U25
    3SRST_BFPGA Bank 503PSCONFIG
    4PS_CLKFPGA Bank 503PSCONFIG
    5PROG_BFPGA Bank 503PSCONFIG
    6INIT_BFPGA Bank 503PSCONFIG
    7DONERed LED, D1
    PS_LP0V85
    Voltage
    Regulator, U12
    9

    2
    DDR
    SRST_
    2V5
    BFPGA Bank 503, U1HPSCONFIG
    3
    Voltage Regulator, U410
    PS_AVCC
    Voltage Voltage
    Regulator, U9
    11DDR_1V2

    4+1.1V_LPDDR4
    Regulator, U15
    12

    5PS_AVTT
    Voltage
    Regulator, U13
    6--
    7PS_FP0V85Regulator,
    U3
    U26
    13

    8PS_
    FP0V85
    LP0V85Voltage Regulator,
    U26
    U12
    14

    9POR_BVoltage
    Translator
    Regulator, U19
    15

    10PS_PLLVoltage Regulator, U23
    16

    11PL_VCCINTVoltage Regulator, U5
    12...15--
    16PL_VCUVoltage Regulator, U24


On-board Peripherals

Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

The TE0821 is equipped with dual Flash Memory, U7, U17.  Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT flash memory chips are provided for FPGA configuration file and data storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

...

Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO
PinSchematicU?? PinNotes
QSPI, U7QSPI, U17Notes
nCSMIO5MIO7
CLKMIO0MIO12
DI/IO0MIO4MIO8
DO/IO1MIO1MIO9
nHOLD/IO3MIO3MIO11
WP/IO2MIO2MIO10


EEPROM

There is a 2Kb EEPROM provided on the module TE0821.

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinSchematicU?? PinNotes
MIO39I2C_SDASDA
MIO38I2C_SCLSCL



Scroll Title
anchorTable_OBP_I2C_EEPROM
titleI2C address for EEPROM

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinI2C AddressDesignatorNotes
MIO38-MIO390x50U25


LEDs

Scroll Title
anchorTable_OBP_LED
titleOn-board LEDs

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorColorConnected toActive LevelNote
D1RedDONELow
D2GreenUSR_LEDHigh
D3RedERR_OUTHigh
D4GreenERR_STATUSHigh


...

Page properties
hiddentrue
idComments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0821 TE0823 SoM has dual 8 Gb volatile DDR4 a 1 GB volatile LPDDR4 SDRAM IC for storing user application code and data.

  • Part number: K4A8G165WB-BIRC IS43LQ32256A
  • Supply voltage: 1.7V ~ 1.2V95V
  • Speed: 2400 3200 Mbps
  • Temperature: -40 ~ 95 °C

...

Power supply with minimum current capability of xx 2.5 A for system startup is recommended.

...

Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


Scroll Ignore

draw.io Diagram
border

true

false
diagramNameTE0823_PWR_PD
simpleViewerfalse
width
linksauto
tbstyle

top

hidden
diagramDisplayName
lboxtrue
diagramWidth

641

640
revision

3

10




Scroll Only


Power-On Sequence

Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTE0823_PWR_PS
simpleViewerfalse
width
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641640
revision36


Scroll Only


Power Rails

Scroll Title
anchorTable_PWR_PR
titleModule power rails.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes
VIN

1, 3, 5

2, 4, 6, 8InputSupply voltage from the carrier board
3.3V-10, 12OutputInternal 3.3V voltage level
3.3VIN13, 15-InputSupply voltage from the carrier board
1.8V39-OutputInternal 1.8V voltage level
JTAG VREF-91OutputJTAG reference voltage.
Attention: Net name on schematic is "3.3VIN"
VCCO_64-7, 9InputHigh performance I/O bank voltage
VCCO_65-5InputHigh performance I/O bank voltage
VCCO_669, 11-InputHigh performance I/O bank voltage


...

Page properties
hiddentrue
idComments
  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B ConnectorsPD:
    6 x 6 SoM LSHM B2B Connectors

Include Page
PD:4 x 5 SoM LSHM B2B ConnectorsPD:
4 x 5 SoM LSHM B2B Connectors

...

Scroll Title
anchorTable_TS_ROC
titleRecommended operating conditions.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

ParameterMinMaxUnitsReference Document
VIN supply voltage3.36VSee TPS82085S datasheet
3.3VIN supply voltage3.33.465VSee LCMXO2-256HC, Xilinx DS925 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS925
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS925
HP I/O banks supply voltage, VCCO0.9501.9VXilinx document DS925
HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range085°CXilinx document DS925, extended grade Zynq temperarure range


...

Scroll Title
anchorFigure_TS_PD
titlePhysical Dimension


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTE0823_TS_PD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth542
revision34


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


...

Scroll Title
anchorFigure_RV_HRN
titleBoard hardware revision number.


Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue
draw.io Diagram
borderfalse
diagramNameTE0823_RV_HRN
simpleViewerfalse
width
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth170
revision2


Scroll Only


...

Scroll Title
anchorTable_RH_DCH
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • Bugfix document style

2021-08-23v.42Pedram Babakhani
  • Bugfix Boot mode
2020-11-02v.40Pedram Babakhani
  • Initial Release

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


...