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The Trenz Electronic TE0823 -01-3PIU1FL is (3PIU1FA /3PIU1FL)  is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ ZU3CGMPSoC, 1 GByte LPDDR4 SDRAM, 128 MByte 8 GB eMMC chip, 2x 64 MB Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.  The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.

The highly integrated modules are All this on a tiny footprint, smaller than a credit card , at the most competitive price. Modules in and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are fully completely mechanically and largely electrically compatible among with each other.

All parts are at least industrial temperature range of -40°C to +85°C. The module . The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Refer to http://trenz.org/te0823-info for the current online version of this manual and other available documentation.

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• SoC/FPGAXilinx Zynq UltraScale+ XCZU3CG-L1SFVC784IApplication Processor: Dual-core ARM Cortex-A53 MPCore
  
  • Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
  Package: SFVC784, SFRC784
  • Device: ZU3ZU2 ...ZU5, *
  • Engine:  EG, CG, EV, *
  • Speed: -1LI (also non-low power assembly options possible)
  • Temperature range: industrial
  • 1, -1L, -2, -2L, 3, *, **
  • Temperature: I, E, *, **
• RAM/Storage
  • 2x  DDR4 SDRAM,
    • Data Width: 32 Bit
    • Size: 16 Gb, *
    • Speed: 3733 Mbps, ***
  • 2x
  RAM/Storage
  • Low power DDR4 on PS with 32 bit data width
  • 128 MByte QSPI boot Flash in dual parallel mode
    • Data Width: 8 Bit
    • Size: 512 Mb Gb, *
  • 1x 8 GByte e.MMC memory with 8 bit data widthMemory
    • Data Width: 8 Bit
    • Size: 32 Gb, *
  • MAC address serial EEPROM with EUI-48 node identity
• On Board
  
  • Lattice LCMXO2
  • PLL SI5338
  • Gigabit Ethernet transceiver PHY
  • MachXO2 CPLD
  • Programmable Clock Generator
  • Hi-speed USB2 ULPI Transceiver
  • 4x LEDS
• Interface
  • 1x GB/s serial GMII interface
  • 1x Hi-speed USB2 ULPI transceiver with full OTG support
  Interface
  • 132 x HP PL 154 x High Performance (HP) und 96 x High Density (HD) I/Os (3 banks)
  • ETH
  • USB
  • 78 x PS MIOs
  • 4 x serial PS GTR transceivers
    4 GTR (for USB3, SATA, PCIe, DP)
    Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:
    • PCI Express interface version 2.1 compliant
    • SATA 3.1 specification compliant interface

    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
    • 14 x PS MIOs
      • MIO for UART
      • thereof 6 MIO for SD card interface (default configuration)
      • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, SATA, PCIe, DP)
      Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:
      • PCI Express interface version 2.1 compliant
      • SATA 3.1 specification compliant interface

      • DisplayPort source-only interface with video resolution up to 4k x 2k

      • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
      • 1 GB/s serial GMII interface
    • 14 x PS MIOs
      • MIO for UART
      • thereof 6 MIO for SD card interface (default configuration)
      • MIO for PJTAG
    • JTAG
    • Ctrl
  • Dimension
    • 4 x 5 cm
  • Notes
    • Rugged for shock and high vibration
    • Evenly spread supply pins for good signal integrity
    • Plug-on module with 2 x 100 pin and 1 x 60 pin Razor Beam High-Speed hermaphroditic Terminal/Socket Strips (low profile, 2,5 mm)

  ...

  • Power
    • All power regulators on board
  • Dimension
    • 40 x 50 mm
  • Note
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination
    • Rugged for shock and high vibration

  BlockDiagram

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  Scroll Title
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  Scroll Ignore scroll-pdf true scroll-office true scroll-chm true scroll-docbook true scroll-eclipsehelp true scroll-epub true scroll-html true draw.io Diagram border false diagramName TE0823_OV_BD simpleViewer false width links auto tbstyle hidden diagramDisplayName lbox true diagramWidth 641 revision 16 Scroll Only Image Added

  Main Components

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  Notes : Picture of the PCB (top and bottom side) with labels of important components Add List below add drawIO object here. Note For more information regarding how to draw a diagramadd board photoes, Please refer to "Diagram Drawing Guidline" .

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  Main Components

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  hidden	true
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  Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

  Note
  For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

  image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

  1. Xilinx Zynq UltraScale+ XCZU3EG, U1
  2. Red LED (ERR_OUT), D3
  3. Green User LED, D2
  4. Green LED (ERR_STATUS), D4
  5. Red LED (DONE), D1
  6. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
  7. 8Gb DDR4, U2-U3
  8. 512 Mbit QSPI flash memory, U7-U17
  9. B2B connector Samtec Razor Beam, JM1
  10. B2B connector Samtec Razor Beam, JM3
  11. Programmable clock generator, U10
  12. USB2.0 Transceiver,  U18
  13. B2B connector Samtec Razor Beam, JM2
  14. 8 GByte eMMC memory, U6
  15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

  Initial Delivery State

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  Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty

  
  

  Scroll Title
  anchor Table_OV_IDS title Initial delivery state of programmable devices on the module
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Storage device name Content Notes QSPI Flash Memory Not programmed eMMC Memory Not programmed Programmable Clock Generator Not programmed CPLD (LCMXO2-256HC) SC0820-02 QSPI Firmware

  Configuration Signals

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  Overview of Boot Mode, Reset, Enables.

  
  

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  anchor Table_OV_BP title Boot process.

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  anchor	Figure_OV_MC
  title	TE0823 main components

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  1. Xilinx Zynq UltraScale+ XCZU3EG, U1
  2. Red LED (ERR_OUT), D3
  3. Green User LED, D2
  4. Green LED (ERR_STATUS), D4
  5. Red LED (DONE), D1
  6. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
  7. 8Gb DDR4, U2-U3
  8. 512 Mbit QSPI flash memory, U7-U17
  9. B2B connector Samtec Razor Beam, JM1
  10. Programmable clock generator, U10
  11. USB2.0 Transceiver,  U18
  12. B2B connector Samtec Razor Beam, JM3
  13. B2B connector Samtec Razor Beam, JM2
  14. 8 GByte eMMC memory, U6
  15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

  Initial Delivery State

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  Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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  anchor Table_OV_IDS title Initial delivery state of programmable devices on the module
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  Storage device name	Content	Notes
  QSPI Flash Memory	Not programmed	eMMC Memory	Not programmed	Programmable Clock Generator	Not programmed	CPLD (LCMXO2-256HC)	SC0820-02 QSPI Firmware

  Configuration Signals

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  Overview of Boot Mode, Reset, Enables.

  MODE Signal State Boot Mode High QSPI* Low SD Card* *changable also with other CPLD Firmware:TE0823 CPLD

  
  

  
  

  Scroll Title
  anchor Table_OV_RST title Reset
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  anchor Table_OV_BP title Boot process.
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MODE Signal State	Boot Mode
  Low	QSPI
  High	SD Card
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  anchor Table_OV_RST title Reset process.
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  Signal	B2B	I/O	Note

  Signals, Interfaces and Pins

  B2B I/O Note RESIN JM2-18 Input

  Signals, Interfaces and Pins

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  Notes : For
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  Notes : For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example: SD USB ETH FMC ... For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example JTAG UART I2C MGT ...

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  Scroll Title
  anchor Table_SIP_B2B title General PL I/O to B2B connectors information
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FPGA Bank B2B Connector I/O Signal Count Voltage Level Notes 24 HD JM2 24x I/O, 12x  LVDS Pairs Variable  Max voltage 3.3V 25 HD JM1 24x I/O, 12x  LVDS Pairs Variable  Max voltage 3.3V 26 HD JM1 24x I/O, 12x  LVDS Pairs Variable  Max voltage 3.3V 44 HD JM2 24x I/O, 12x  LVDS Pairs Variable Max voltage 3.3V 65 HP JM2 18x I/O, 9x LVDS Pairs Variable Max voltage 1.8V 65 HP JM3 16x I/O, 8x LVDS Pairs Variable Max voltage 1.8V 505 GTR JM3 16x I/O, 8x LVDS Pairs - 4x lanes 505 GTR CLK JM3 1x Diff Clock - 501 MIO JM1 15 I/O 3.3V

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  Scroll Title
  anchor Table_SIP_USB title General overview of the USB PHY signals
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true  PHY Pin ZYNQ Pin B2B Name Notes ULPI MIO52..63 - Zynq USB0 MIO pins are connected to the USB PHY. REFCLK - - 52.000000 MHz from on-board oscillator (U14). REFSEL[0..2] - - Reference clock frequency select, all set to GND selects 52.000000 MHz. RESETB MIO25 - Active low reset. CLKOUT MIO52 - Connected to 1.8V, selects reference clock operation mode. DP, DM - OTG_D_P, OTG_D_N USB data lines routed to B2B connector JM3 pins 47 and 49. CPEN - VBUS_V_EN External USB power switch active high enable signal, routed to JM3 pin 17. VBUS - USB_VBUS Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55. ID - OTG_ID For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.

  MIO Pins

  I2C Interface

  On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C0 by default. Addresses for on-board I²C slave devices are listed in the table below:

  you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

  Example:

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  anchor Table_SIP_I2C title Address table of the I2C bus slave devices
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  MIO Pin	Connected to	B2B	Notes
  MIO12...14	SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK	J2	QSPI
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  anchor Table_SIP_MIOs title MIOs pins
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  MIO Pin	Connected to	B2B	Notes
  0...5	QSPI Flash, U7	-	SPI Flash
  7...12	QSPI Flash, U17	-	SPI Flash
  13...23	eMMC, U6
  24	ETH Transceiver, U8	-	ETH_RST
  25	USB2.0 Transceiver, U18	-	OTG_RST
  26...33	User MIO	JM1
  34...37	N.C	-	N.C
  38...39	EEPROM, U25	-	I2C_SDA/SCL
  40...45	N.C	N.C	46...51	SD Card	JM1	52...63	USB2.0 Transceiver, U18	-	63...77	Ethernet Transceiver, U8	-

  Test Points

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  you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

  Example:

  I2C Device I2C Address Notes Si5338A PLL 0x70 - EEPROM 0x50 -

  MIO Pins

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  hidden true id Comments
  you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin Connected to B2B Notes MIO12...14 SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK J2 QSPI

  
  

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  anchor Table_SIP_MIOs title MIOs pins
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin Connected to B2B Notes 0...5 QSPI Flash, U7 - SPI Flash 7...12 QSPI Flash, U17 - SPI Flash 13...23 eMMC, U6 24 ETH Transceiver, U8 - ETH_RST 25 USB2.0 Transceiver, U18 - OTG_RST 26...33 User MIO JM1 34...37 N.C - N.C 38...39 EEPROM, U25 - I2C_SDA/SCL 40...45 N.C N.C 46...51 SD Card JM1 52...63 USB2.0 Transceiver, U18 - 63...77 Ethernet Transceiver, U8 -

  Test Points

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  hidden true id Comments
  you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point Signal B2B Notes 10 PWR_PL_OK J2-120

  
  

  Scroll Title
  anchor Table_SIP_TPs title Test Points Information
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Test Point Signal Connected to Notes 1 PS_LP0V85 Regulator, U12 2 SRST_B FPGA Bank 503, U1H PSCONFIG 3 PS_AVCC Regulator, U9 4 +1.1V_LPDDR4 Regulator, U15 5 PS_AVTT Regulator, U13 6 - - 7 PS_FP0V85 Regulator, U26 8 PS_LP0V85 Voltage Regulator, U12 9 POR_B Voltage Regulator, U19 10 PS_PLL Voltage Regulator, U23 11 PL_VCCINT Voltage Regulator, U5 12...15 - - 16 PL_VCU Voltage Regulator, U24

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  anchor	Table_SIP_TPs
  title	Test Points Information

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  On-board Peripherals

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  Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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  anchor Table_OBP title On board peripherals
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  Quad SPI Flash Memory

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  Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

  QSPI Flash U7, U17 EEPROM U25 DDR4 SDRAM U2,U3 GigaBit Ethernet U8 USB2.0 Transceiver U18 eMMC Memory U6 Oscillators U32, U14, U11 Programmable Clock Generator U25 CPLD U21 LEDs D1...3

  Quad SPI Flash Memory

  The TE0821 is equipped with dual Flash Memory, U7, U17.  Two quad SPI compatible serial bus flash memory chips are provided for FPGA configuration file and data storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

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  Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

  
  

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  anchor Table_OBP_SPI title Quad SPI interface MIOs and pins
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  anchor Table_OBP_SPI title Quad SPI interface MIOs and pins
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin Schematic U?? Pin Notes

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  Notes QSPI, U7 QSPI, U17 nCS MIO5 MIO7 CLK MIO0 MIO12 DI/IO0 MIO4 MIO8 DO/IO1 MIO1 MIO9 nHOLD/IO3 MIO3 MIO11 WP/IO2 MIO2 MIO10

  EEPROM

  There is a 2Kb EEPROM provided on the module TE0821.

  Scroll Title
  anchor Table_OBP_EEP title I2C EEPROM interface MIOs and pins
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin Schematic U?? Pin Notes MIO39 I2C_SDA SDA MIO38 I2C_SCL SCL

  
  

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  anchor Table_OBP_I2C_EEPROM title I2C address for EEPROM
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin I2C Address Designator Notes MIO38-MIO39 0x50 U25

  LEDs

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  anchor Table_OBP_LED title On-board LEDs
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Color Connected to Active Level Note D1 Red DONE Low D2 Green USR_LED High D3 Red ERR_OUT High D4 Green ERR_STATUS High

  DDR4 SDRAM

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  Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

  The TE0823 SoM has a 1 GB volatile LPDDR4 SDRAM IC for storing user application code and data.

  • Part number: IS43LQ32256A
  • Supply voltage: 1.7V ~ 1.95V
  • Speed: 3200 Mbps
  • Temperature: -40 ~ 95 °C

  Gigabyte Ethernet

  On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U11).

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  anchor Table_OBP_ETH title Ethernet PHY to Zynq SoC connections
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true U8 Pin  Schematic Connected to Note MDIP0...3 PHY_MDI0...3 B2B, JM1 MDC ETH_MDC MIO76 MDIO ETH_MDIO MIO77 S_IN S_IN B2B, JM3 S_OUT S_OUT B2B, JM3 TXD0..3 ETH_TXD0...3 MIO65...68 TX_CTRL ETH_TXCTL MIO69 TX_CLK ETH_TXCK MIO64 RXD0...3 ETH_RXD0...3 MIO71...74 RX_CTRL ETH_RXCTL MIO75 RX_CLK ETH_RXCK MIO70 LED0...2 PHY_LED0...2 FPGA Bank 66 RESETn ETH_RST MIO24

  
  Clock Sources

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  anchor Table_OBP_CLK title Osillators
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Description Frequency Note U11 MEMS Oscillator 25 MHz U14 MEMS Oscillator 52 MHz U32 MEMS Oscillator 80 MHz

  USB2.0 Transceiver

  Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

  eMMC Flash Memory

  eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

  Programmable Clock Generator

  There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

  A 25.00 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.

  Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

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  anchor Table_OBP_EEPPCLK title I2C EEPROM interface MIOs and pinsProgrammable Clock Generator Inputs and Outputs
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true
  MIO Pin	Schematic	U?? Pin	Notes
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  anchor Table_OBP_I2C_EEPROM title I2C address for EEPROM
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  MIO Pin	I2C Address	Designator	Notes

  ...

  U25 Pin Signal Connected to Direction Note IN0..1 CLK_IN JM3 IN IN2 CLK_25M Oscillator, U11 IN SCL I2C_SCL EEPROM,U25 INOUT SDA I2C_SDA EEPROM,U25 INOUT CLK0 CLK0 JM3 OUT CLK1 B505_CLK3 FPGA Bank 505 IN CLK2 B505_CLK1 FPGA Bank 505 IN CLK3 CLK3_N IN

  Power and Power-On Sequence

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  hidden true id Comments
  In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: Power on-sequence Power distribution Voltage monitoring circuit Note For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

  Power Supply

  Power supply with minimum current capability of 2.5 A for system startup is recommended.

  Power Consumption

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  anchor Table_OBPPWR_LEDPC title On-board LEDsPower Consumption
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  Designator	Color	Connected to	Active Level	Note

  DDR3 SDRAM

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  Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

  The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

  ...

  sortEnabled false cellHighlighting true Power Input Pin Typical Current VIN TBD*

  * TBD - To Be Determined

  Power Distribution Dependencies

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  anchor TableFigure_OBPPWR_ETHPD title Ethernet PHY to Zynq SoC connectionsPower Distribution
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  U?? Pin	Signal Name	Connected to	Signal Description	Note

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  diagramName TE0823_PWR_PD simpleViewer false width links auto tbstyle hidden diagramDisplayName lbox true diagramWidth 640 revision 10 Scroll Only Image Added

  Power-On Sequence

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  Designator	Description	Frequency	Note
  MHz	MHz	KHz

  Programmable Clock Generator

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  PWR_PS title Power Sequency

  Scroll Ignore draw.io Diagram border false diagramName TE0823_PWR_PS simpleViewer false width links auto tbstyle hidden diagramDisplayName lbox true diagramWidth 640 revision 6 Scroll Only Image Added

  Power Rails

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  anchor Table_OBPPWR_PCLKPR title Programmable Clock Generator Inputs and OutputsModule power rails.
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  U?? Pin	Signal	Connected to	Direction	Note
  IN0	IN1	IN2	IN3	XAXB	SCLK	SDA	OUT0	OUT1	OUT2	OUT3	OUT4	OUT5	OUT6	OUT7	OUT8/OUT9

  Power and Power-On Sequence

  ...

  hidden	true
  id	Comments

  In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit

  Note
  For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

  Power Rail Name B2B Connector JM1 Pin B2B Connector JM2 Pin B2B Connector JM3 Pin Direction Notes VIN 1, 3, 5 2, 4, 6, 8 Input Supply voltage from the carrier board 3.3V - 10, 12 Output Internal 3.3V voltage level 3.3VIN 13, 15 - Input Supply voltage from the carrier board 1.8V 39 - Output Internal 1.8V voltage level JTAG VREF - 91 Output JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" VCCO_64 - 7, 9 Input High performance I/O bank voltage VCCO_65 - 5 Input High performance I/O bank voltage VCCO_66 9, 11 - Input High performance I/O bank voltage

  Bank Voltages

  Power Supply

  Power supply with minimum current capability of xx A for system startup is recommended.

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  Scroll Title
  anchor Table_PWR_PCBV title Power ConsumptionZynq SoC bank voltages.
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  Power Input Pin	Typical Current
  VIN	TBD*

  * TBD - To Be Determined

  Power Distribution Dependencies

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  anchor	Figure_PWR_PD
  title	Power Distribution

  Bank           Schematic Name Voltage Notes 24 HD VCCO_HD24_24 Variable  Max voltage 3.3V 25 HD Variable  Max voltage 3.3V 26 HD VCCO_HD25_26 Variable  Max voltage 3.3V 44 HD VCCO_HD24_44 Variable Max voltage 3.3V 65 HP VCCO_65 Variable Max voltage 1.8V 66 HP VCCO_66 1.8V 500 PSMIO VCCO_PSIO0_500 1.8V 501 PSMIO VCCO_PSIO1_501 3.3V 502 PSMIO VCCO_PSIO2_502 1.8V 503 PSCONFIG VCCO_PSIO3_503 1.8V 504 PSDDR DDR_1V2 1.2V

  
  Board to Board Connectors

  Page properties
  hidden true id Comments
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  4 x 5 SoM LSHM B2B Connectors 4 x 5 SoM LSHM B2B Connectors

  Technical Specifications

  Absolute Maximum Ratings

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  Power-On Sequence

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  title	Power Sequency

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  anchor Table_PWRTS_PRAMR title Module power rails.PS absolute maximum ratings
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  Power Rail Name	B2B Connector JM1 Pin	B2B Connector JM2 Pin	B2B Connector JM3 Pin	Direction	Notes

  Bank Voltages

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  anchor	Table_PWR_BV
  title	Zynq SoC bank voltages.

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  Bank          

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  Voltage

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  id	Comments

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  style widths sortByColumn 1 sortEnabled false cellHighlighting true Symbols Description Min Max Unit VIN supply voltage -0.3 7 V See EN6347QI and TPS82085SIL datasheets 3.3VIN supply voltage -0.1 3.630 V Xilinx DS925 and TPS27082L datasheet PS I/O supply voltage, VCCO_PSIO -0.5 3.630 V Xilinx document DS925 PS I/O input voltage -0.5 VCCO_PSIO + 0.55 V Xilinx document DS925 HP I/O bank supply voltage, VCCO -0.5 2.0 V Xilinx document DS925 HP I/O bank input voltage -0.55 VCCO + 0.55 V Xilinx document DS925 PS GTR reference clocks absolute input voltage -0.5 1.1 V Xilinx document DS925 PS GTR absolute input voltage -0.5 1.1 V Xilinx document DS925 Voltage on SC CPLD pins -0.5 3.75 V Lattice Semiconductor MachXO2 datasheet Storage temperature -40 +85 °C See eMMC datasheet

  Recommended Operating Conditions

  Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  use "include page" macro and link to the general B2B connector page of the module series,

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  Technical Specifications

  Absolute Maximum Ratings

  Description

  Scroll Title
  anchor Table_TS_AMRROC title PS absolute maximum ratingsRecommended operating conditions.
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true	Symbols

  Parameter	Min	Max	Units

  Unit

  Reference Document
  VIN supply voltage	3.3	6

  VVV

  V

  V