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Table of Contents |
Overview
The Trenz Electronic
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TE0823-01-3PIU1FL is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ ZU3CG, 1 GByte LPDDR4 SDRAM, 128 MByte Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.
All this on a tiny footprint, smaller than a credit card, at the most competitive price. Modules in 4 x 5 cm form factor are fully mechanically and largely electrically compatible among each other.
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Refer ... module ... based on Xilinx ...Refer to http://trenz.org/tec0850te0823-info for the current online version of this manual and other available documentation.
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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- <Replace for module use "SoC/FPGA" for Carrier "Modules">
- RAM/Storage
- On Board
- Interface
- Power
- Dimension
- Notes
Block Diagram
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For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" . |
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| anchor | Figure_OV_BD |
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| title | TE0823 block diagram |
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Main Components
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Notes :
- Picture of the PCB (top and bottom side) with labels of important components
- Add List below
| Note |
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For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" . |
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| anchor | Figure_OV_MC |
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| title | TE0823 main components |
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- Xilinx Zynq UltraScale+ XCZU3CG-L1SFVC784I
- Application Processor: Dual-core ARM Cortex-A53 MPCore
- Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
- Package: SFVC784
- Device: ZU3
- Engine: CG
- Speed: -1LI (also non-low power assembly options possible)
- Temperature range: industrial
- RAM/Storage
- Low power DDR4 on PS with 32 bit data width
- 128 MByte QSPI boot Flash in dual parallel mode
- 8 GByte e.MMC memory with 8 bit data width
- MAC address serial EEPROM with EUI-48 node identity
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY
- Hi-speed USB2 ULPI transceiver with full OTG support
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, SATA, PCIe, DP)
Four high-speed serial I/O (HSSIO) interfaces supporting following protocols: - 14 x PS MIOs
- MIO for UART
- thereof 6 MIO for SD card interface (default configuration)
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, SATA, PCIe, DP)
Four high-speed serial I/O (HSSIO) interfaces supporting following protocols: - 14 x PS MIOs
- MIO for UART
- thereof 6 MIO for SD card interface (default configuration)
- MIO for PJTAG
- JTAG
- Ctrl
- Dimension
- Notes
- Rugged for shock and high vibration
- Evenly spread supply pins for good signal integrity
- Plug-on module with 2 x 100 pin and 1 x 60 pin Razor Beam High-Speed hermaphroditic Terminal/Socket Strips (low profile, 2,5 mm)
Block Diagram
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| anchor | Figure_OV_BD |
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| title | TE0823 block diagram |
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| revision | 5 |
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Main Components
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- ...
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Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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Storage device name
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Content
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Notes
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Quad SPI Flash
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- Overview of Boot Mode, Reset, Enables.
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| orientation | portrait |
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| sortDirection | ASC |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE Signal State | Boot Mode |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortEnabled | false |
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Signal | B2B | I/O | Note |
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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| Scroll Title |
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| anchor | Figure_OV_MC |
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| title | TE0823 main components |
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| border | false |
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| diagramName | TE0823_OV_MC |
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| diagramWidth | 641 |
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| revision | 2 |
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- Xilinx Zynq UltraScale+ XCZU3EG, U1
- Red LED (ERR_OUT), D3
- Green User LED, D2
- Green LED (ERR_STATUS), D4
- Red LED (DONE), D1
- 10/100/1000 Mbps energy efficient ethernet transceiver, U8
- 8Gb DDR4, U2-U3
- 512 Mbit QSPI flash memory, U7-U17
- B2B connector Samtec Razor Beam, JM1
- Programmable clock generator, U10
- USB2.0 Transceiver, U18
- B2B connector Samtec Razor Beam, JM3
- B2B connector Samtec Razor Beam, JM2
- 8 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
Initial Delivery State
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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Storage device name | Content | Notes |
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Quad SPI Flash |
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| | System Controller CPLD |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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| anchor | Table_SIPOV_JTGBP |
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| title | JTAG pins connectionBoot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG B2B Connector | TMS | TDI | TDO | TCK | JTAG_EN | |
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signals, Interfaces and Pins
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| you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
| MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPINotes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
| Scroll Title |
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| anchor | Table_SIP_MIOsB2B |
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| title | MIOs pins | General PL I/O to B2B connectors information |
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| scroll-scroll-tablelayout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Connected to | B2B | Notes |
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Test Points
| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMX.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
| Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 | | Scroll Title |
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortEnabled | false |
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| Test Point | Signal | Connected to | Notes |
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JTAG Signal | B2B Connector |
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| TMS |
| | TDI |
| | TDO |
| | TCK |
| | JTAG_EN |
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MIO Pins
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Page properties |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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| Scroll Title |
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| anchor | Table_SIP_MIOs |
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| title | MIOs pins |
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: | Test Point | Signal | B2B | Notes |
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| 10 | PWR_PL_OK | J2-120 |
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.
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| Scroll Title |
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| anchor | Table_OBPSIP_SPITPs |
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| title | Quad SPI interface MIOs and pinsTest Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| Scroll Title |
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| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MIO Pin | Schematic | U? Pin | Notes
| Scroll Title |
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| anchor | Table_OBP_I2C_RTC |
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| title | I2C Address for RTCOn board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address| Chip/Interface | Designator | Notes |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| Scroll Title |
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| Scroll Title |
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| anchor | Table_OBP_EEPSPI |
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| title | I2C EEPROM Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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EEPROM
| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROMEEP |
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| title | I2C address for EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Scroll Title |
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| anchor | Table_OBP_LEDI2C_EEPROM |
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| title | On-board LEDsI2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Designator | Color | Connected to | Active Level | Note |
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| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| U?? Pin | Signal Name | Connected to | Signal Description | Note |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CANCLK |
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| title | CAN Tranciever interface MIOsOsillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Bank| Schematic | U?? Pin | Notes | D-Tx | Driver Input | R-Rx | Reciever Output | |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Description | Frequency | Note |
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| MHz |
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| MHz |
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| KHz |
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Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using
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Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
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| Scroll Title |
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Ignore |
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| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power-On Sequence
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| anchor | Figure_PWR_PS |
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| title | Power Sequency |
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| Scroll Ignore |
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| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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| draw.io Diagram |
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| border | true |
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| diagramName | TE0823_PWR_PD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | top |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 1 |
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Power-On Sequence
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| Scroll Title |
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| anchor | Figure_PWR_VMCPS |
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| title | Voltage Monitor CircuitPower Sequency |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| diagramName | TE0823_PWR_PS |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | top |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 1 |
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|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed Image Added |
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Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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| Page properties |
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
| Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Technical Specifications
Absolute Maximum Ratings
| Include Page |
|---|
| PD:4 x 5 SoM LSHM B2B Connectors |
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| PD:4 x 5 SoM LSHM B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
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| Scroll Title |
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| anchor | Table_TS_AMR |
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| title | PS absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit | V |
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Recommended Operating Conditions
...
| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V°C | See Xilinx ???? datasheet. |
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| V°C | See Xilinx ???? datasheet. | V | See Xilinx
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Physical Dimensions
...
mm. Please download the assembly diagram for exact numbers.
Mating
...
Physical Dimensions
Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
...
| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| |
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| diagramName | TE0823_TS_PD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | top |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 1 |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed Image Added |
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Currently Offered Variants
...
| Scroll Title |
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| anchor | Table_VCP_SO |
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| title | Trenz Electronic Shop Overview |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Revision History
Hardware Revision History
...
| Scroll Title |
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| anchor | Figure_RV_HRN |
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| title | Board hardware revision number. |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| |
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| diagramName | TE0823_RV_HRN |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | top |
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| lbox | true |
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| diagramWidth | 254 |
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| revision | 1 |
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|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
|---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed Image Added |
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Document Change History
| Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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| Scroll Title |
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
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| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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-- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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Disclaimer
...
| anchor | Figure_OV_BD |
|---|
| title | TExxxx block diagram |
|---|
| Scroll Ignore |
|---|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
|---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
| Scroll Title |
|---|
| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
|
| | Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | -- | all | | Page info |
|---|
| infoType | Modified users |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
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Disclaimer
| Include Page |
|---|
| IN:Legal Notices |
|---|
| IN:Legal Notices |
|---|
|
| draw.io Diagram |
|---|
| border | true |
|---|
| diagramName | TE0823_OV_BD |
|---|
| simpleViewer | false |
|---|
width | | links | auto |
|---|
| tbstyle | top |
|---|
| lbox | true |
|---|
| diagramWidth | 641 |
|---|
| revision | 4 |
|---|
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