• Last modified: May 08, 2025

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Overview

The Trenz Electronic TE0950-02 is a powerful adaptive SoC evaluation board, equipped with an AMD Versal™ AI (Edge) device. Furthermore, the board is equipped with up to 8GB DDR4 SDRAM, 128 MByte SPI Flash and an  eMMC for configuration and data storage as well as powerful switching power supplies for all required voltages. Inputs and outputs are provided by robust, flexible and cost-effective high-speed connectors.

Refer to http://trenz.org/te0950-info for the current online version of this manual and other available documentation.

Key Features

  • SoC
    • AMD Versal™ AI device 1)
      • Package: A784
      • Device:  VE2202, VE2302, VM1102 1)
      • Speed: -1, -2, -3 1)
      • Temperature: I, E 1)
  • RAM/Storage
    • DDR4 SDRAM
      • Data width: 64bit
      • Size: def. 8GB, up to 8 GByte possible 1)
      • Speed: up to 3200Mb/s 2)
    • 128 MByte SPI Flash (primary boot option)
      • Data width: 8bit
      • size: def. 128MB, up to 512MB possible 1)
    • MicroSD card (primary boot option)
    • e.MMC (secondary boot option) 1)
      • Data width: 8bit
      • size: def. 32GB 1)
    • EEPROM with MAC-address
  • On Board
    • AMD Artix™ 7 FPGA as configurable Levelshifter/MUX for FMC and other 3.3 V IOs
      • 32 MByte SPI Flash
      • 1 dip switch
      • 2 LEDs
    • USB 2.0 Host/Device/OTG (type Micro A/B connector)
    • USB JTAG + UART Micro-USB B
    • Gigabit Ethernet RJ45
    • Output
      • 2 LEDs (1 x MIO, 1 x PL)
    • Input
      • 1 push button (PL)
      • 2 dip switches (2 x MIO)
      • Reset button
  • Interface
    • zQSFP
      • 4 GTYP Transceiver
    • 2 x CRUVI HS
      • each optimized for 4 Lane MIPI, one with reduced pinout
    • 2 x CRUVI LS
    • CSI-2 connector
      • optimized for camera, 2 lane MIPI
    • FMC
      • 4 GTYP Transceiver
      • 34 LA diff pairs to Levelshifter/MUX
  • Power
    • 12 V plug
  • Dimension
    • 150 mm x 120 mm
  • Notes
    • 1) depends on assembly version
    • 2) depends on used DDR4
    • 3) productions within 2023 are equipped with engineering samples (AMD Vivado ES licence needed)

Block Diagram


TE0950 block diagram

Main Components

TE0950 main components
  1. SoC (Versal) U1
  2. DDR4 U8, U9, U10, U11
  3. eMMC U25
  4. dual QSPI Configuration Flash (Versal) U23, U24
  5. ETH Phy U31
  6. MAC EEPROM U35
  7. USB 2.0 Phy U27
  8. Jumper (USB Device/Host/OTG) J5
  9. Artix FPGA (Levelshifter/MUX for FMC IOs) U13
  10. OSPI Configuration Flash (Artix) U14
  11. FTDI JTAG/UART to USB Bridge U15
  12. FTDI Configuration EEPROM U17
  13. zQSFP U12/J1
  14. LPC FMC J3
  15. CRUVI HS J10, J11
  16. CRUVI LS J12, J13
  17. CSI CAM Connector J15
  18. SD-CARD Slot J4
  19. RJ45 ETH jack J9
  20. micro USB A/B Connector J8
  21. micro USB B Connector (JTAG/UART) J2
  22. 4 Pin FAN Connector J17
  23. Power Input Jack J14
  24. Reset Push Button S3
  25. User Push Button S1
  26. Dip Switches (JTAG Selection) S4
  27. Dip Switches (Bootmode, User) S2
  28. Dip Switches (FMC VADJ Selection, User) S5
  29. LEDs (Power) D8, D9, D10
  30. LEDs (Status/User) D0, D1, D2, D3 D4, D6, D11
  31. 1x6 JTAG Header J18 (optional)

Initial Delivery State

Storage device name

Content

Notes

DDR4 SDRAMnot programmed


eMMCnot programmed


dual Quad SPI Flash (Versal)

not programmed


MAC EEPROMnot programmed besides factory programmed MAC address


FTDI EEPROMFTDI configuration for JTAG/UART with AMD Vivado compatible license
Quad SPI Flash (Artix)Template Design with basic functionalityDesign has to be adapted to use case.
Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector TypeDesignatorInterfaceIO CNTNotes
B2B J3FMC

4x MGT Transeiver
34 DIFF / 68 SE
4x CLK, CLKDIR, I2C, PG

MGTs tested with 25.777Gbps (Maximum for speedgrade)
FMC LA pins from/to Artix. Artix FPGA has to be configured for use case.
CLK and management signals connected to Artix.

B2BJ10CRUVI HS

12 DIFF / 24 SE
4 SE
8 SE

Full pinout, MIPI 4 Lanes optimized (XPIO)
(XPIO)
connected to Artix @3.3V
B2BJ11CRUVI HS

9 DIFF / 18 SE
2 SE
8 SE

Reduced pinout, MIPI 4 Lanes optimized (XPIO)

(XPIO)
connected to Artix @3.3V

B2BJ12CRUVI LS8 SEHD bank 302 @3.3V
B2BJ13CRUVI LS8 SEHD bank 302 @3.3V
CONJ1, U12zQSFP4x MGT Transeiver
5 SE, I2C		MGTs tested with 25.777Gbps (Maximum for speedgrade),
management signals connected to Artix.
CONJ15CSI-2 CAM3 DIFF / 6 SE
4 SE		MIPI 2Lanes (XPIO),
(I2C and GPIO) to HD Bank 302 @3.3V
CONJ9GB ETH4 DIFFLPD
CONJ8micro USB2.0 A/B1 DIFFHost/Device/OTG set J5 according for HW configuration
CONJ2micro USB2.0 B1 DIFFJTAG/UART via FTDI
CONJ4micro SD 2.07 SEprimary boot option, routed via levelshifter U26
CONJ174 pin FAN2 SEFor SoC FAN with Tacho and PWM signals connected to Artix.
CONJ18JTAG4SEnot assembled, footprint compatible to 1x6 2,54mm pitch header
Board Connectors


Test Points

Test PointSignalNotes1)

TP32

GNDGND

TP29

12V12V
TP175V05V
TP163V33.3V
TP43, TP44GTYP_AVCC0.92V
TP46, TP47GTYP_AVTT1.2V
TP45GTYP_AVCC_AUX1.5V
TP48A_3V33.3V
TP191V01.0V
TP423V3_FMC3.3V
TP40FMC_VADJ

1.2V, S5A-C: OFF,OFF, OFF
1.8V, S5A-C: ON,OFF, OFF
2.5V, S5A-C: ON,ON, OFF
3.3V, S5A-C: ON,ON, ON

TP181V81.8V
TP39V_VCCAUX1.5V
TP41C_VADJ1.2V
TP35DDR_1V21.2V
TP33DDR_2V52.5V
TP36DDR_VTT0.6V

TP37

VREFA0.6V
TP38V_VCC_SOC

0.8V (low (L) and mid (M) voltage devices)

0.88V (high (H) voltage devices) 

TP34V_VCC_CORE

0.7V (low (L) voltage devices) 
0.8V (mid (M) voltage devices) 
0.88V (high (H) voltage devices) 

TP1V_VCC_BATTInput for VCC_BAT supply when R21 removed. Default (R21 assembled) GND.
TP2V_FUSEInput for V_FUSE supply when R43 removed. Default (R43 assembled) GND.
TP3DDR4-TEN_0pulled-down to GND
TP4DDR4-TEN1pulled-down to GND
TP5DDR4-TEN2pulled-down to GND
TP6DDR4-TEN3pulled-down to GND
TP20PHY_LED2Function dependent on ETH PHY (U31) configuration.
TP21I2C_PMC_SCL@1.8V
TP23I2C_PMC_SDA@1.8V
TP22DCDC_5V0_SCL@3.3V Levelshifted I2C_PMC_SCL signal
TP24DCDC_5V0_SDA@3.3V Levelshifted I2C_PMC_SDA signal
TP25I2C1_SCL@1.8V
TP26I2C1_SDA@1.8V
TP27I2C_SYSMON_SCL@1.8V
TP28I2C_SYSMON_SDA@1.8V
TP7TCKJTAG TCK (Versal and Artix)
TP12TMSJTAG TCK (Versal and Artix)
TP10V_TDOJTAG TDO
TP8FTDI_TDIJTAG TDI
TP9A_TDIJTAG TDI Artix, connected to FTDI_TDI  via DIP S4A
TP11V_TDIJTAG TDI Versal, connected to FTDI_TDI  via DIP S4B
TP13A_TDOJTAG TDO Versal, connected to VTDI  via DIP S4C
TP14F_UART_TX@3.3V, from Versal, levelshifted UART1_TX signal, to FTDI
TP15F_UART_RX@3.3V, from FTDI, levelshifted UART1_RX signal to Versal
TP31-Sense input of reset chip U38, connected to PG_GTYP_AVTT @3.3V via R203
TP30FAULTn_12V@12V, Fault signal of input protection U37


Test Points Information

On-board Peripherals

Chip/InterfaceDesignatorConnected ToNotes
Versal SoCU1

-

REV01, REV02, REV03-EGBE21A: Engineering Sample

DDR4 SDRAMU8, U9, U10, U11Versal XPIO


dual parallel QSPIU23, U24Versal PMC/MIO

primary boot option

optional instead OSPI at U23 and U24 not fitted, also some resistors have to be changed, compare schematics 

GB ETH PHYU31Versal MIO
USB PHYU27Versal MIOUSB2.0
OscillatorU4, U5Versal XPIO2x 200Mhz, DDR4 controller, User
OscillatorU6, U7Versal GTYP REFCLK156.25MHz, 125MHz, for QSFP MGTs.
eMMCU25Versal PMC/MIO

secondary boot option

EEPROMU35
for MAC. I2C PS, Address 50H
User Dip 3xS2C, S2D

Versal MIO


User LED 2x D0
D1

Versal MIO
Versal HD

both green;
Silkscreen lable: LED0 and LED1

Push ButtonS1Versal HD
Artix FPGAU13
  • Versal XPIO
    (14 DIFF / 28 SE)
  • FMC (J3) LA pins
  • QSFP (J1, U12) config signals
  • CRUVI HS (J10, J11) 3.3V signals
Configurable levelshifter/MUX for FMC and other 3.3V periphery configuration signals
QSPIU14Artixconfiguration Memory for Artix
User LED 2xD2, D3ArtixD2 green and D3 red;
Silkscreen lable: LED2 and LED3
User DipS5DArtix
On board peripherals

Configuration and System Control Signals

ComponentLabel 
'Silkscreen' or on -Component-

Signal Name

Direction1)Description
LED D11 (red)'ERROR'V_ERROROUTVersal Error  → signal 'low' → LED 'ON'
LED D4 (red)'DONE'V_DONEOUTVersal configuration Done → signal 'high' → LED 'OFF'
Dip switch S2A 'BOOT' -1-V_MODE1IN

Select primary boot mode:

JTAGQSPI32SD card (SD1 2.0)OSPI
OFFONOFFOFF
OFFOFFONOFF
OFFOFFOFFON


Dip switch S2B'BOOT' -2-V_MODE02IN
Dip switch S2C'BOOT' -3-V_MODE3IN
DIP switch S4A'JTAG' -1-FTDI_TDI, A_TDIIN

Select JTAG:

Artix-Versal in chainVersal only
ONOFF
OFFON
ONOFF


DIP switch S4B'JTAG' -2-FTDI_TDI, V_TDIIN
DIP switch S4C'JTAG' -3-A_TDO, V_TDIIN
LED D6 (red)  'DONE''DONE'A_DONEOUTArtix configuration Done → signal 'high' → LED 'OFF'
LED D7 (green) 'UART''UART'F_UART_LEDOUTUART activity → signal 'low' → LED 'ON'
Push button S3 'RESET''RESET'MRINOn press resets configuration of Versal and Artix by pulling V_POR_B, A_PROG_B signals via reset chip U38 low.
LED D9 (green) '12V''12V'12VOUT'ON' when 12V after power protection available
LED D8 (green) '5V''5V'5V0OUT'ON' when 5V are available
LED D10 (green) '3.3V_FMC'3V3_FMCOUT'ON' when 3.3V_FMC available
DIP switch S5A 'FMC_VADJ' -1-FB_FMC_VADJIN

Select FMC_VADJ:

1.2V1.8V2.5V3.3V
OFFONONON
OFFOFFONON
OFFOFFOFFON


DIP switch S5B 'FMC_VADJ' -2-FB_FMC_VADJIN
DIP switch S5C 'FMC_VADJ' -3-FB_FMC_VADJIN

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Controller signal.

Power and Power-On Sequence


Power Rails

Power Rail Name/ Schematic NameConnector + PinDirection1)Notes
12V_INJ14.1INBoard Power
5V0

J12.12, J13.12,
J10.60, J11.60

OUT

CRUVI LS and HS 5V, shared with onboard 5V supplies and with further switch (U29) for rail USB_VBUS_SUP via jumper (J5) connectable to USB (J8).

3V3J12.10, J13.10, J3.D32OUTQSFP, CRUVI LS 3.3V, CSI-2 CAM, FMC_VAUX, shared with VERSAL VCCO Bank 302 and onboard peripherals.
C_VADJJ10.36, J11.36OUTCRUVI HS IO @1.2V, shared with VERSAL VCCIO XPIO Bank 703.
A_3V3J10.4, J10.9, J11.4, J11.9OUTCRUVI HS 3.3V, shared with ARTIX VCCIO Bank 14 and onboard peripherals.
12VJ3.C35, J3.C37OUTFMC, derived from 12V_IN after input protection. Shared with onboard peripherals.
3V3_FMCJ3.C39, J3.D36, J3.D38, J3.D40OUTFMC
FMC_VADJJ3.E39, J3.F40, J3.G39, J3.H40OUTFMC 1.2V - 3.3V, Selectable by dip settings.

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Module power rails.

Recommended Power up Sequencing

Power up sequencing is handled board internally. No further interaction needed. For details See Schematic page 4 Power Diagram.

Board to Board Connectors

Following B2B connectors for board extensions are available:

  • CRUVI,
    • Please see also CRUVI documentation at CRUVI.com.
    • More extensions are available at the Trenz electronic CRUVI.
    • CRUVI modules use on bottom side:
      • TMMH-106-04-F-DV-A-M as Low Speed connectors, (12 pins, 6 per row) 
      • ST4-30-1.50-L-D as High Speed connectors, (60 pins, 30 per row) 

      CRUVI carrier use on top side: 

      • CLT-106-02-F-D-A-K as Low Speed connectors , (12 pins, 6 per row) 
      • SS4-30-3.50-L-D as High Speed connectors, (60 pins, 30 per row)
      Connector Mating height

      Mating height of the high speed connectors is 5mm. The low speed connectors mate correctly within a range from 4.78 mm to 5.29 mm.

      Current Rating

      Current rating of High Speed B2B connectors is 1.6A per pin (2 pins powered).

      Current rating of Low Speed B2B connectors is 4.1A per pin (2 pins powered).

      Speed Rating

      There is no data available for the connectors actual used here. Data available for other stacking heights of same connectors is summarized in the folllowing table:

      ConnectorSpeed ratings
      ST4/SS4 single ended (4mm stacking height!)13.5GHz / 27 Gbps
      ST4/SS4 differential (4mm stacking height!)15.5 GHz / 31 Gbps
      TMMH/CLT single ended (4.77mm stacking height!)5.5GHz / 11 Gbps
      Connector speed ratings
      Operating Temp Range

      All connectors are specified for a temp. range of -55 °C to 125 °C.

  • FMC
    • Unable to render {include} The included page could not be found.

Technical Specifications

Absolute Maximum Ratings *)

Power Rail Name/ Schematic NameDescriptionMinMaxUnit
12V_INMain power supply-2030V
Absolute maximum ratings

*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  • Variants of modules are described here: Article Number Information
  • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
  • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
  • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
  • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


ParameterMinMaxUnitsReference Document
12V_IN11.013.0V-
Recommended operating conditions.


Physical Dimensions

  • Module size: 150 mm × 120 mm.  Please download the assembly diagram for exact numbers.

PCB thickness: 1.6 mm.

Physical Dimension

Currently Offered Variants 

Trenz shop TE0950 overview page
English pageGerman page
Trenz Electronic Shop Overview

Revision History

Hardware Revision History


DateRevisionChangesDocumentation Link
2023-02-09REV01Initial revisionREV01
2023-06-20REV02

  1. Inverted card detect (pullup-> pulldown)

  2. Increased number of capacitors on VTT (C388,C389)

  3. Added 1K pullup on FAULTn_12V (R5)

  4. Added 4-pin connector J17 for FAN and correspoding circuit. PWM  and TACHO connected to ARTIX

  5. VERSAL JTAG connection corrected

  6. Added CRUVI connector description on silkscreen

  7. Changed polarity for CSI2-CAM diff pairs

  8. Update from library

  9. Changed R266 to 12K and added R281

  10. Changed enable 3V3 after 5V0 (R99), Pullup on PG_5V0 connected to 5V0 rail.

  11. Replaced C256 (2,2µF) by 2x 1µF

  12. Set R131 and R132 to not fitted (2023-08-18)
REV02

2024-01-17















2024-02-15

REV03

1. Added OSPI compatibility, renamed sheet (QSPI_SD_eMMcC -> SD_eMMcC) and added sheet QSPI_OSPI.
2. Added D12 and pull-up R170 for correct reset levels, set R131 and R132 to assembled
3. Added Pin header J18 for direct JTAG access
4. Moved V_L22 diff. pair to clock capable pins on Atrix
5. Small improvements of MGT routing, added anti-pads, optimized VIAs, increased clearance.
6. Versal changed from Engeniering Sample to production (pre-production for ES9749) chips
7. Replaced U20 by IR3899A DCDC
8. Removed U34  (I2C levelshifter for former U20)
9. Added Common mode chock L29, Fuse F1, C288, C289 and D13 to 12V input rail.
10. Moved PM1, PM2, PM5, PM6
11. Silkscreen dip switch description:
      Added boot mode "OSPI"  selectable via dip S2C, former connection (User PMC MIO27) moved to S4D.
        - added OSPI boot mode,
        - S4D is user dip switch connected to Versal PMC (MIO27)
12. Updated all components from lib


13. Set ZigZag Placeholder for JTAG (J18) to not fitted to make it more clear  that there is no header fitted
14. Updated AMD Versal (U1) Schematic Symbol 

REV03
Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Board hardware revision number.

Document Change History

DateRevisionContributorDescription

v.19

Martin Rohrmüller

  • Updated layout of configuration signal table for better readability

v.17

Martin Rohrmüller

  • Added silkscreen labels in On-board Peripherals: LED0..3
  • Added column 'Label' in table 'Configuration signals' for more clearity
  • Added Hardware Revision history: REV03 point 13 and 14.

v.15

Martin Rohrmüller

Updated MGTs tested speed for REV03

 

v.12

Martin Rohrmüller

Updated to REV03

v.11

Martin Rohrmüller

Typos corrected

v.9

Martin Rohrmüller

  • initial revision
Document change history.

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Product Disclaimer

Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.

Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.



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