Download PDF version of this document.


Overview

The Trenz Electronic TE0817 is an industrial grade SoM, which integrates an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, QSPI Boot Flash memory for configuration and operation, multiple MGT transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable IO's is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to https://trenz.org/te0817-info for the current online version of this manual and other available documentation.

Key Features

  • SoC
    • Device 1):                      ZU4 / ZU5 / ZU7
    • Engine 1):                      CG / EG / EV
    • Speedgrade 1):              -1 / -2 / -3
    • Temperature Range 1):  Extended / Industrial
    • Package:                        FBVB900
  • RAM/Storage
    • 4x DDR4 SDRAM 8 Gbit (4x 512 M x 16 bit) 2) 3)
    • 2x QSPI Flash 512 Mbit (with XiP support) 2)
    • EEPROM with unique EUI-48 ™ / MAC address
  • On Board
    • Programmable clock generator with Jitter feedback loop
    • Oscillators for SoC PS, SoC RTC and the clock generator
    • SoM status LED
  • Interface
    • Trenz 4 x 6 SoM 4x B2B connector (Samtec ADM6) socket:
      • MIO:      65x SE
      • IO HD: 156x SE / 72x DIFF @ variable voltage
      • IO HP:   48x SE / 24x DIFF @ variable voltage
      • MGT:       4x GTR (RX/TX)
                     16x GTH (RX/TX)
  • Power
    • Power rails for Programmable Logic, MGT transceiver, Low and Full Power domains individual controllable
    • Monitoring for most Voltage Rails
  • Dimension
    • 76.0 mm x 52.0 mm
  • Notes
    1) Available as assembly variant or upon request.
    2) Other sizes/devices, which are pin/package-compatible, upon request.
    3) Up to 8 GByte are possible with a maximum bandwidth of 2400 MBit/s.

Block Diagram


 


TE0817 block diagram

Main Components

TE0817 main components
  1. SoC, U1
  2. DDR4, U2, U3, U9, U12
  3. Quad SPI Flash, U7, U17
  4. Connector, J1, J2, J3, J4
  5. EEPROM, U11
  6. Clock Generator, U5
  7. LED - Status DONE, D1

Initial Delivery State

Storage device name

Designator

Content

Notes

SoCU1Not programmed
Quad SPI FlashU7 / U17Not programmed
EEPROMU5Not programmed besides factory programmed MAC address.
Programmable Clock GeneratorU11Not programmed
Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector TypeDesignatorInterfaceIO countNotes
B2BJ1MGT PL12 x MGT (RX/TX)
B2BJ1HP52 SE / 24 DIFF
B2BJ2MGT PS2 x MGT CLK
B2BJ2CLKDIFF CLK
B2BJ2MGT PL4 x MGT (RX/TX)
B2BJ2MGT PS4 x MGT (RX/TX)
B2BJ2CFGJTAG
B2BJ2CFGMODE
B2BJ3HD48 SE / 24 DIFF
B2BJ3MGT PL3 x MGT CLK
B2BJ3CLKDIFF CLK
B2BJ3MIO65 GPIO
B2BJ4HP104 SE / 48 DIFF
Board Connectors

Test Points


Test

Point

REV02

REV01

Signal


Notes

Top

Bottom

Signal

TP1


x

PLL_SCL

Pulled-up to SI_PLL_1V8

TP2


x

PLL_SDA

Pulled-up to SI_PLL_1V8

TP3


x

DDR4-TEN

Not used

Pulled-down to GND

TP4

x


VTT

Not used


TP5


x

GND


TP6


x

TCK


TP7


x

TDI


TP8


x

TDO


TP9


x

TMS


TP10

x


LP_0V85

Not used


TP11

x


FP_0V85

Not used


TP12


x

PL_VCCINT


TP13

x


PS_PLL

Not used


TP14

x


PS_GT_1V0

Not used


TP15


x

FP_0V85


TP16


x

DDR_2V5


TP17


x

DCDC_2V0


TP18


x

DDR_PLL


TP19


x

PS_GT_1V0

Not used


TP20


x

PL_VCU


TP21

x


PS_AUX

Not used


TP22

x


PS_AVCC

Not used


TP23


x

VTT

VTT


TP24


x

AUX_R


TP25


x

AVTT_R


TP26


x

AVCC_R


TP27


x

PS_PLL


TP28


x

PS_AVTT


TP29


x

PS_AUX


TP30


x

PS_AVCC


TP31


x

LP_0V85


TP32


x

GND


TP33

x


PS_AVTT



TP34

x


DDR_PLL



TP35

x


DDR_2V5



TP36

x


VREFA

N


TP37


x

VREFA

o


TP38

x


3.3VIN

t


TP39

x


LP_DCDC



TP40

x


PL_VCCINT

u


TP41

x


DCDCIN

s


TP42

x


DCDC_2V0

e


TP43

x


PL_DCIN

d


TP44

x


PL_GT_1V45



TP45


x

PL_GT_1V45



TP46

x


GT_DCDC



TP47

x


PL_GT_1V15



TP48


x

PL_GT_1V15



TP49

x


PLL_3V3



TP50

x


AUX_R

N


TP51

x


PSBATT

o


TP52

x


AVCC_R

t


TP53

x


AVTT_R



TP54

x


VCCO_47

u


TP55

x


PL_VCU

s


TP56

x


VCCO_48

e


TP57

x


1V8_REFIN

d


TP58


x

1V8_REFIN



TP59

x


VCCO_64



TP60

x


1V25_REF



TP61


x

1V25_REF



TP62

x


VCCO_65



TP63

x


VCCO_66



TP64

x


PLL_VDDA

N


TP65


x

PLL_VDDA

o


TP66

x


PLL_VDD

t


TP67


x

PLL_VDD



TP68

x


PS_1V8

u


TP69

x


PL_1V8

s


TP70

x


SI_PLL_1V8

e


TP71


x

SI_PLL_1V8

d


TP72

x


DDR4_1V2



Test Points Information

On-board Peripherals

Chip/InterfaceDesignatorConnected ToNotes

DDR4 SDRAM

U2 / U3 / U9 / U12
  • SoC PS

Quad SPI Flash

U7 / U17
  • SoC PS

EEPROM

U11
  • I2C
  • B2B J2

Clock Generator

U5
  • SoC
  • B2B J2, J3

Oscillator

U25
  • Clock Generator
25 MHz

Oscillator

U32
  • SoC
33⅓ MHz

Oscillator

Y1
  • Clock Generator
50 MHz

Oscillator

Y2
  • SoC RTC
32.768 kHz
On board peripherals

Configuration and System Control Signals

Control signals represent hardware defined logic states, for final state consider the firmware and reference designs.

Control Signals and Buses


Signal Name

Connector.Pin

Direction1)Description
POR_OVERRIDEJ1.A45INOverride power-on reset delay 2).
PG_PLL_1V8J2.A30OUTSI_PLL_1V8 power rail powered-up.
ERR_OUTJ2.A31OUTPS error indication 2).
ERR_STATUSJ2.A34OUTPS error status 2).
LP_GOODJ2.A35OUTLow-power domain powered-up. Pulled up to 3.3VIN.
PLL_SCLJ2.A36INI2C clock
PLL_SDAJ2.A37IN/OUTI2C data
PG_VCUJ2.A40OUTVCU power rail powered-up.
EN_PSGTJ2.A41INEnable GTR transceiver power-up.
TCK / TDI / TDO / TMSJ2.A44 / J2.A45 /
J2.A46 / J2.A47
Signal-dependent

JTAG configuration and debugging interface.

JTAG reference voltage: PS_1V8

PG_PSGTJ2.B29OUTGTR transceivers powered-up.
PROG_BJ2.B30IN/OUTPower-on reset 2). Pulled-up to PS_1V8.
SRST_BJ2.B33INSystem reset 2). Pulled-up to PS_1V8.
INIT_BJ2.B34IN/OUTInitialization completion indicator after POR 2). Pulled-up to PS_1V8.
PG_PLJ2.B37OUTProgrammable logic powered-up.
EN_FPDJ2.B38INEnable full-power domain power-up.
PG_FPDJ2.B41OUTFull-power domain powered-up.
EN_LPDJ2.B42INEnable low-power domain power-up.
PG_DDRJ2.B45OUTDDR power supply powered-up.
DONEJ2.B46OUTPS done signal 2). Pulled-up to PS_1V8.
EN_DDRJ2.B47INEnable DDR power-up.
EN_GT_LJ2.C30INNot connected.
MRJ2.C31INManual reset.
PLL_SEL0J2.C32INPLL clock selection.
PLL_RSTJ2.C33INPLL reset.
EN_PLJ2.C35INEnable programmable logic power-up.
EN_GT_RJ2.C36INEnable GTH transceiver power-up.
PLL_FDECJ2.C37INPLL Frequency decrementation.
MODE3..0J2.C44 / J2.C45 / J2.C46 / J2.C47INBoot mode selection 2):
  • JTAG
  • QUAD-SPI (32 Bit)
  • SD1 (2.0)
  • eMMC (1.8 V)
  • SD1 LS (3.0)

Supported Modes depends also on used Carrier.

EN_PLL_PWRJ2.D29INEnable PLL power supply.
PLL_FINCJ2.D30INPLL Frequency incrementation.
PLL_LOLnJ2.D31OUTLoss of lock status.
PLL_SEL1J2.D32INPLL clock selection.
PG_GT_RJ2.D33OUTGTH Transceivers powered-up.
PSBATTJ2.D37INPS RTC Battery supply voltage 2) 3).
PUDC_BJ2.D38INConfiguration pull-ups setting 2). Pulled-up to PL_1V8.
DX_P / DX_NJ2.D45 / J2.D46-SoC temperature sensing diode pins 2).

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

2) See UG1085 for additional information.

3) See Recommended Operating Conditions.

Controller signal.

Power and Power-On Sequence

Power Rails

Power Rail Name/ Schematic NameConnector.PinDirection1)Notes
DCDCINJ2.A57 / J2.A58 / J2.A59 / J2.A60 / J2.B57 / J2.B58 / J2.B59 / J2.B60 / J2.C57 / J2.C58 / J2.C59 / J2.C60 / J2.D57 / J2.D58 / J2.D59 / J2.D60 / IN
LP_DCDCJ2.A50 / J2.A51 / J2.A52 / J2.B50 / J2.B51 / J2.B52 / J2.C50 / J2.C51 / J2.C52 / J2.D50 / J2.D51 / J2.D52IN
PL_DCINJ1.C56 / J1.C57 / J1.C58 / J1.C59 / J1.C60 / J1.D56 / J1.D57 / J1.D58 / J1.D59 / J1.D60IN
PLL_3V3J3.A55IN
GT_DCDCJ3.A59 / J3.A60 / J3.B59 / J3.B60 / J3.C59 / J3.C60 / J3.D59 / J3.D60 /IN
3.3VINJ1.A54 / J1.A55 / J1.B55 / J1.B56IN
PS_BATTJ2.D37IN
VCCO_47J3.C19 / J3.C20 / J3.D20 / J3.D21IN
VCCO_48J3.C7 / J3.C8 / J3.D8 / J3.D9IN
VCCO_64J4.B21 / J4.B39IN
VREF_64J4.B30IN
VCCO_65J4.C21 / J4.C39IN
VREF_65J4.C30IN
VCCO_66J1.A32 / J1.A33IN
VREF_66J1.A41IN

PL_1V8

J1.C32 / J1.C33 / J1.D33 / J1.D34OUT
PS_1V8J2.C34 / J2.D34 / J3.A56 / J3.B56 / J3.C56 / J3.D56OUT
DDR_1V2J2.D47OUT

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Module power rails.

Recommended Power up Sequencing

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.

SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes






Basic SoM management
0---Configuration signal setup.See Configuration and System Control Signals.
1 1)PSBATT1.2 V to 1.5 V-Battery connection.Battery Power Domain usage. When not used, tie to GND.
13.3VIN3.3 V (± 5 %)-Management power supply.Management module power supply. 0.5 A recommended.
PLL (Usage of external clocks and needed for GTH / GTR Transceiver clocking)
1 1)GT_DCDC3.20 V to 3.63 V
or
5.0 V (±10 %) 2)

GTH transceiver power supply.Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
1 1)EN_PLL_PWR-PD 3), GNDPLL power enable.
1 1)PG_PLL_1V8-PU 3), 3.3 VPLL power good status.
Processing System (PS)
2.1Low-power domain:Bring-up for low-power domain PS.
2.1.1LP_DCDC

3.20 V to 3.63 V
or
5.0 V (±10 %) 2)

-Low-power domain power supply.Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2EN_LPD-PU 3), 3.3 VLow-power domain power enable.
2.1.3LP_GOOD-PU 3), 3.3 VLow-power domain power good status.Module power-on sequencing for low-power domain finished.
2.2Full-power domain:Bring-up for full-power domain PS.Full-power PS domain needs powered low-power PS domain.
2.2.1DCDCIN

3.10 V to 3.63 V
or
5.0 V (±10 %) 2)

 


Full-power domain and GTR transceiver power supply.Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2EN_FPD3.3 V-Full-power domain power enable.
2.2.3PG_FPD-PU 3), 3.3 VFull-power domain power good status.Module power-on sequencing for full-power domain finished.
2.2.4EN_DDR3.3 V-DDR memory power enable.
2.2.5PG_DDR
PU 3), 3.3 VDDR memory power good status.Module power-on sequencing for DDR memory finished.

2.3

GTR TransceiverProcedure for GTR transceiver starting.PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1EN_PSGT3.3 V-GTR transceiver power enable.
2.3.2PG_PSGT-PU 3), 3.3 VGTR transceiver power good status.Module power-on sequencing for GTR transceiver finished.
Programmable Logic (PL)
2.1Programmable Logic (PL)Procedure for PL starting.PS and PL can be started independently.
2.1.1PL_DCIN

2.97 V to 3.63 4)
or
5.0 V (±10 %) 2)

-Programmable logic power supply.Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2EN_PL-PU 3), 3.3 VProgrammable logic power enable.
2.1.3PG_PL-PU 3), 3.3 VProgrammable logic power good status.Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.1.4VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 5)-Module bank voltages.Enable bank voltages after PG_PL deassertion.
2.1.5PG_VCU-PU 3), 3.3 VVCU power good status.
2.2GTH TransceiverProcedure for GTH / GTY transceiver starting.PL transceiver usage needs powered PL and low-power PS domain.
2.2.1GT_DCDC3.20 V to 3.63 V
or
5.0 V (±10 %) 2) 
-GTH transceiver power supply.Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2EN_GT_R3.3 V-GTH / GTY transceiver power enable.
2.2.3PG_GT_R-PU 3), 3.3 VGTH / GTY transceiver power good status.

1) Optional

2) Dependent on the assembly option a higher input voltage may be possible. 

3) On module

4) This value depends highly on DCDC U4. Higher values may be possible with different DCDCs. For more information consult schematic and according datasheets.

5) See DS925 for additional information.

Baseboard Design Hints

Board to Board Connectors

5.2 x 7.6 cm UltraSoM+ modules use four Samtec AcceleRate HD High-Density Slim Body Arrays on bottom side.
  • 4x ADM6-60-01.5-L-4-2 (legacy) or ADM6-60-01.5-L-4-0 (240 pins, 60 per row)
    •  Mates with ADF6-60-03.5-L-4-2 (legacy) or ADF6-60-03.5-L-4-0

5.2 x 7.6 cm UltraSoM+ carrier use four Samtec AcceleRate HD High-Density Slim Body Arrays on top side.

  • 4x ADF6-60-03.5-L-4-2 (legacy) or ADF6-60-03.5-L-4-0 (240 pins, 60 per row)
    • Mates with ADM6-60-01.5-L-4-0 (legacy) or ADM6-60-01.5-L-4-2
Features
  • Board-to-Board connector 240-pins, 60 contacts per row
  • Pitch:           0.025" (0.635 mm)
  • Data Rate:

    • ADM6-XX-XX.X-X-X-2: 56 Gbps

    • ADM6-XX-XX.X-X-X-0: 64 Gbps

  • Mates with: ADM6/APF6
  • Insulator Material: Black LCP
  • Contact Material:  Copper Alloy
  • Plating:                 Au or Sn over 50 µ" (1.27 µm) N
  • Operating Temperature Range: -55 ºC to +125 ºC
  • Lead-Free solderable: Yes
  • RoHS Compliant:        Yes
Connector Stacking height

When using the standard type on baseboard and module, the mating height is 5 mm. Other mating heights are possible by using connectors with a different height:

Order numberREF numberSamtec NumberTypeContribution to stacking heightComment
30095REF-30095ADM6-60-01.5-L-4-2Module connector1.5 mmStandard connector used on modules (legacy)
- -ADM6-60-01.5-L-4-0Module connector1.5 mmAlternative connector
31137REF-31137ADF6-60-03.5-L-4-2Baseboard connector3.5 mmStandard connector used on carrier (legacy)
--ADF6-60-03.5-L-4-0Baseboard connector3.5 mmAlternative connector
Connectors.
Connector Speed Ratings

The AcceleRate HD High-Density connector speed rating depends on the stacking height; please see the following table:

ConnectorStacking heightSpeed rating
ADM6-XX-XX.X-X-X-25 mm56 Gbps
ADM6-XX-XX.X-X-X-05 mm64 Gbps
Speed rating.
Current Rating

Current rating of Samtec AcceleRate HD High-Density B2B connectors is 1.34 A per pin (4 pins powered).

Connector Mechanical Ratings
  • Shock:      100G, 6 ms Sine
  • Vibration:  7.5G random, 2 hours per axis, 3 axes total



Technical Specifications

Absolute Maximum Ratings *)

Power Rail Name/ Schematic NameDescriptionMinMaxUnit
DCDCINMicromodule Power-0.37.0V
LP_DCDCMicromodule Power-0.36.0V
PL_DCIN 1)Micromodule Power-0.3

7.0

V
PLL_3V3PLL power supply-0.53.8V
GT_DCDCMicromodule Power-0.36.0V
3.3VINMicromodule Power-0.33.6V
PS_BATTRTC / BBRAM-0.52.0V
VCCO_47HD IO Bank power supply-0.53.4V
VCCO_48HD IO Bank power supply-0.53.4V
VCCO_64HP IO Bank power supply-0.52.0V

VCCO_65

HP IO Bank power supply-0.52.0V
VCCO_66HP IO Bank power supply-0.52.0V
VREF_64Bank input reference voltage-0.52.0V
VREF_65Bank input reference voltage-0.52.0V
VREF_66Bank input reference voltage-0.52.0V

1) REV01 can only withstand max. 4.0 V. The limitation depends on DCDC U4. Higher values are possible with different DCDCs. For more information consult schematic and according datasheets.

PS absolute maximum ratings

*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

  • Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
  • Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
  • Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

  • Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
  • Cooling solution, active and or passive cooling.
  • Climate or environmental conditions besides ambient temperature range.
  • Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

Classification of the module can be looked up here: Zynq Ultrascale+ based modules (MPSoC, RFSoC) i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).

ParameterMinMaxUnitsReference Document
DCDCIN 1)3.103.63VSchematic
4.55.5VSchematic
LP_DCDC 1)3.203.63VSchematic
4.55.5VSchematic
PL_DCIN 1) 2)2.973.63VSchematic
4.55.5VSchematic
PLL_3V33.1353.465VSchematic
GT_DCDC 1)3.203.63VSchematic
4.55.5VSchematic
3.3VIN3.133.60VSchematic
PS_BATT1.21.5VSee FPGA datasheet.
VCCO_471.1643.399VSee FPGA datasheet.
VCCO_481.1643.399VSee FPGA datasheet.
VCCO_640.971.854VSee FPGA datasheet.

VCCO_65

0.971.854VSee FPGA datasheet.
VCCO_660.971.854VSee FPGA datasheet.
VREF_640.61.2VSee FPGA datasheet.
VREF_650.61.2VSee FPGA datasheet.
VREF_660.61.2VSee FPGA datasheet.

1) Note was removed

2) This value depends highly on REV01 DCDC U4. Higher values may possible with different DCDCs or different revision. For more information consult schematic and according datasheets.

Recommended operating conditions.

Physical Dimensions

  • Module size: 76.0 mm × 52.0 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

  • PCB thickness: 1.74 mm ±10 %.

Physical dimension

Currently Offered Variants 

Trenz shop TE0817 overview page*
English pageGerman page

*)  Module article name encoding table: Zynq Ultrascale+ based modules (MPSoC, RFSoC)

Trenz Electronic Shop Overview

Revision History

Hardware Revision History

The hardware revision number can be found on the PCB board together with the module's model number, separated by a dash.

Board hardware revision number


DateRevisionChangesDocumentation Link
2024-0402
  1. Changed DCDC (U13) from EN6347QI to MPM3860GQW-Z and updated according circuit.

  2. Connected DDR4-TEN signals together for U2, U3, U9, and U12 and pulled them low via 499 Ohm resistor R127. Added testpoint TP3 for signal DDR4-TEN.

  3. Changed voltage rail from 1.35 V to 1.45 V via adaption voltage divider resistor R30 and changed voltage rail name PL_GT_1V35 to PL_GT_1V45.

  4. Changed voltage rail from 1.05 V to 1.15 V via adaption voltage divider resistors R33 and R35 and changed voltage rail name PL_GT_1V05 to PL_GT_1V15.

  5. Added diode D2 between U41 pin 3 net MR and voltage rail 3.3VIN.

  6. Added capacitors C202 ... C205 for VTT voltage rail VTT.

  7. Added resistors R124 (default: not fitted) and R125 to supply U4 VCC either from PL_DCIN or from 3.3VIN.

  8. Changed resistor R76 from 4.22 kOhm to 9.09 kOhm to set current limit to nearly 14.3 A for U4.

  9. Changed inductor (L9) from XGL4030-301MEC to XGL5030-351MEC.

  10. Added remote sense option (default: not fitted):

    1. R126 for U30.

    2. R128 for U29.

    3. R129 for U31.

  11. Added decoupling capacitors:

    1. C208 for U4.

    2. C211, C212, and C213 for U6.

    3. C216 for U10.

    4. C214 for U26.

    5. C215 for U27.

    6. C210 for U34.

    7. C196 for U39.

    8. C197 for U40.

    9. C198 for U42.

    10. C199 for U41.

    11. C200 for U44.

    12. C201, C206, and C207 for U1.

  12. Added pull-up resistors for HOLD (R130) and WP (R131) signals for Flash U7.

  13. Added pull-up resistors for HOLD (R132) and WP (R133) signals for Flash U17.

  14. Changed capacitor (C132) from 1 nF, X7R to 1.2 nF, NP0.

  15. Changed 10 nF capacitor (C112) from 16 V, 0402 to 10 V, 0201.

  16. Changed 100 nF capacitors (C37, C95, C96, C130, and C131) from 6.3 V, X5R, 0201 to 50 V, X7R, 0402.

  17. Changed capacitor (C76, C77, C134, C195) from 1 µF, 16 V to 2.2 µF, 10 V.

  18. Changed capacitor (C129, C140, C141, C142, C143, C144, C145, C146, C147, C148, C153) from 10 µF, 16 V to 22 µF, 10 V.

  19. Changed 22 µF capacitor (C70, C73, C74, C75) from 0805 to 0603.

  20. Changed 22 µF capacitor ( C78, C80, C81, C82, C83, C84, C85, C86, C87, C110, C152, C154, C178) from 6.3 V to 10 V.

  21. Changed 100 Ohm resistors (R7, R10) from 0201, 0.05 W to 0402, 0.063 W.

  22. Changed resistor R77 from 12 kOhm to 10 kOhm.

  23. Changed resistors R41 and R58 from 2 kOhm to 2.49 kOhm.

  24. Added testpoints TP4, TP10, TP11, TP13, TP14, TP19, TP21, TP22, TP33 ... TP72.

  25. Added UKCA logo.

  26. Updated from library.

  27. Changed signal trace length.

  28. Updated documentation.

REV02

PCN
PCN

-01First Production ReleaseREV01
Hardware Revision History

Document Change History

DateRevisionContributorDescription

  • Updated TRM to revision 4.3.8
  • Connectors - Removed note
  • Rev. History - Picture rotated
  • Power-On Seq. - Enhanced readability

2025-07-24

v.23

Kilian Jahn

  • Updated Voltage Rails in Recommended Operating Conditions

2024-04-17

v.21

ED

  • Updated to board REV02.

2023-03-02

v.17

Martin Rohrmüller

  • Corrected max possible DDR4 assembly option

2023-01-16

v.14

ED

  • Fixed issue in absolute maximum ratings
2022-11-08v.13ED
  • Initial Document

--

all

  • --
Document change history.

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Product Disclaimer

Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.

Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.



Table of contents