TE0807 TRM

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Overview

The Trenz Electronic TE0807 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+ MPSoC, up to 8 GBytes of DDR4 SDRAM via 64bit wide data bus, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed stacking connections. All this in a compact 5.2 x 7.6 cm form factor, at the competitive price.

Key Features

• MPSoC: ZYNQ UltraScale+ ZU7EV 900-pin package
• Memory
  - 64bit DDR4, 8 GByte maximum
  - Dual SPI boot Flash in parallel, 512 MByte maximum
• User I/Os
  - 65 x PS MIOs, 48 x PL HD GPIOs,  156 x PL HP GPIOs (3 banks)
  - Serial transceivers: 4 x GTR + 16 x GTH
  - Transceiver clocks inputs and outputs
  - PLL clock generator inputs and outputs
• Si5345 - 10 output PLL
• All power supplies on board, single 3.3V power source required
  - LPD, FPD, PL separately controlled power domains
• Support for all boot modes (except NAND) and scenarios
• Support for any combination of PS connected peripherals
• Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
• B2B connectors: 4 x 160 pin

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components

1. Xilinx ZYNQ UltraScale+ ZU7EV-1FBVB900 MPSoC, U1
2. EN63A0QI 12A PowerSoC DC-DC converter, U4
3. TI TPS72018 LDO @1.8V, U6
4. TI TPS74401 LDO @0.9V, U14
5. TI TPS74401 LDO @1.2V, U28
6. TI TPS72018 LDO @1.8V, U6
7. Quarz Crystal @50.000MHz, Y1
8. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
9. TI TPS74801 LDO @1.8V, U10
10. TI TPS74801 LDO @0.9V, U8
11. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U12
12. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U9
13. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U2
14. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U3
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
18. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
19. 1.8V, 512 Mbit QSPI flash memory ,U17
20. 1.8V, 512 Mbit QSPI flash memory, U7
21. TI TPS72018 LDO @1.8V, U27

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

The boot device and mode of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins accessible on B2B connector J2:

Table 2: Boot mode pins on B2B connector J2.

Following boot modes are possible on the TE0808 UltraScale+ module by generating the corresponding 4-bit code by the pins PS_MODE0 ... PS_MODE3 (little-endian alignment):

Table 3: Selectable boot modes by dedicated boot mode pins

For functional details see  ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).

Signals, Interfaces and Pins

Board to Board (B2B) connectors

The TE0807 MPSoC SoM has four Board to Board (B2B) connectors with 160 contacts per connector.

Each connector has a specific arrangement of the signal pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq UltraScale+ MPSoC like I/O banks, interfaces and Gigabit transceivers
or to the on-board peripherals.

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS pairs or single ended I/O's to the B2B connectors.

Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-02 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the B2B pin-out, please refer to the Pin-out table. 

The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.

MGT Lanes

The Xilinx Zynq UltraScale+ MPSoC device used on the TE0807 module has 20 high-speed data lanes (Xilinx GTH / GTR transceiver). All of them are wired directly to B2B connector. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 5: MGT lanes

There are 2 clock sources for the GTH and GTR transceivers. The clock inputs of the MGT transceivers are connected directly to the B2B connectors, so the clock can be provided by the carrier board. The second clock source is provided by the on-board clock generator Si5345A (U5). As there are no capacitive coupling of the data and clock lines that are connected to the B2B connectors, these may be required on the user’s PCB depending on the application.

Table 6: MGT reference clock sources

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

Table 7: B2B connector pin-out of JTAG interface.

Configuration Bank Control Signals

The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

Table 8: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

Table 9: B2B connector pin-out of analog input pins

Quad SPI Interface

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

Table 10: PS MIO pin assignment of the Quad SPI Flash memory ICs.

Default PS MIO Mapping

Table 11: TE0807-02 PS MIO mapping

On-board Peripherals

Flash

The TE0807 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

Table 12: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-02 SoM is equipped with with four DDR4-2400 SDRAM modules with up to 8 GByte memory density. The SDRAM modules are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64bit wide data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

Programmable PLL Clock Generator

Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

Table 13: Programmable PLL clock generator input/output.

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

Table 14: B2B connector pin-out of Si5345A programmable clock generator.

Si5345 OTP can only be programmed two times, as different user configurations may required different setup TE0808 is normally shipped with blank OTP.
For more information refer to Si5345 at SiLabs.

Oscillators

The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

Table 15: On-board osciallators

MAC Address EEPROMs

There is one Microchip 24AA025E48 serial EEPROMs (U11) present containing a globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The device are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROM accessible over I²C bus on B2B connector J2-92 (PLL_SDA)  / J2-90 (PLL_SCL).

On-board LEDs

Table 16: LED's description.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 17: Maximum current of power supplies. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0807 module equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular external DC-DC converters.

The Processing System contains three Power Domains:

• Battery Power Domain (BBRAM and RTC)
• Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
• Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0807 SoM, following power domains can be powered up individually with power rails available on the B2B connectors:

• Full-power domain, supplied by power rail DCDCIN
• Low-power domain, supplied by power rail LP_DCDC
• Programmable logic, supplied by power rail PL_DCIN
• Battery power domain, supplied by power rail PS_BATT

Each power domain has its own enable and power good signals. The power rail GT_DCDC is needed to generate the voltages for the Multi Gigabit Transceiver units of the Zynq UltraScale+ MPSoC.

Power Distribution Dependencies

The power rails DCDCIN, LP_DCDC, PL_DCIN, PS_BATT have to be powered up on the assigned pins of the B2B connectors as listed on the section "Power Rails". Except 'PS_BATT' (see section "Recommended Operation Conditions"), all power-rails can be powered from 3.3V power sources (also share the same source, if power domain control is not required).

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.

Power-On Sequence

The TE0807 SoM meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The on-board voltages of the TE0807 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be powered up at three steps.

1. Low-Power Domain (LPD) and on-board Si5345A programmable clock generator supply voltage
2. Programmable Logic (PL) and Full-Power Domain (FPD)
3. GTH, PS GTR transceiver and DDR memory

Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance has to be asserted.

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

Operation Conditions of the DC-DC Converter Control Signals

The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good signals need external pull-up resistors.

Table 18: Recommended operation conditions of DC-DC converter control signals.

Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808 SoM.

Voltage Monitor Circuit

The voltages LP_DCDC and LP_0V85 are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.

Power Rails

Table 19: TE0807-02 power rails

Bank Voltages

Table 20: TE0807-02 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table 21: Module absolute maximum ratings

Recommended Operating Conditions

Table 22: Recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 4mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Revision History

Hardware Revision History

Table 23: Hardware revision history table

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	initial document

Table 24: Document change history

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