TEB0724 TRM

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Table of Contents

Overview

The Trenz Electronic TEB0724-01 is a carrier board for the TE0724 and compatible modules.

Key Features

Samtec 160 pin board to board connector
10x 2x6 Pin Pmods, (8 usable as dual Pmods, 1x single Pmod, 1x I²C Pmod)
MicroUSB to JTAG/UART bridge
CAN screw terminal
RJ45 Gigabit Ethernet MagJack connector
6x LED, 2x Push Buttons on FPGA
1 LED and 1 Push Button on PS
Power and Reset Push Buttons
On-board Power Protection Circuit and Power on LED

Block Diagram

Figure 1: TEB0724 block diagram

Main Components

Figure 2: TEB0724 main components

Table 1: TE0724-01 main components.

Initial Delivery State

Not programmed.

Storage device name	Content	Notes
..	..
OTP Flash area	Empty	Not programmed.

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

MODE Signal State	Boot Mode
High or open	SD Card
Low or ground	QSPI Interface

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

Bank	Type	B2B Connector	I/O Signal Count	Bank Voltage	Notes

64	HR	JM1	8 I/Os	3.3V	On-module power supply.
66	HP	JM3	16 I/Os, 8 LVDS pairs	B66_VCCO	Supplied by the carrier board.

Table x: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables.

The configuration of the PS I/Os MIOx, MIOx ... MIOx, ... depend on the carrier board peripherals connected to these pins.

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Lane	Bank	Type	Signal Name	B2B Pin	FPGA Pin
0	225	GTH	MGT_RX0_P MGT_RX0_N MGT_TX0_P MGT_TX0_N	JM3-8 JM3-10 JM3-7 JM3-9	MGTHRXP0_225, Y2 MGTHRXN0_225, Y1 MGTHTXP0_225, AA4 MGTHTXN0_225, AA3
1	225	GTH	MGT_RX1_P MGT_RX1_N MGT_TX1_P MGT_TX1_N	JM3-14 JM3-16 JM3-13 JM3-15	MGTHRXP1_225, V2 MGTHRXN1_225, V1 MGTHTXP1_225, W4 MGTHTXN1_225, W3
..	..	..	..	..	..
4	224	GTH	MGT_RX4_P MGT_RX4_N MGT_TX4_P MGT_TX4_N	JM1-12 JM1-10 JM1-6 JM1-4	MGTHRXP0_224, AH2 MGTHRXN0_224, AH1 MGTHTXP0_224, AG4 MGTHTXN0_224, AG3
5	224	GTH	MGT_RX5_P MGT_RX5_N MGT_TX5_P MGT_TX5_N	JM1-24 JM1-22 JM1-18 JM1-16	MGTHRXP1_224, AF2 MGTHRXN1_224, AF1 MGTHTXP1_224, AF6 MGTHTXN1_224, AF5
..	..	..	..	..	..

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

Clock signal	Bank	Source	FPGA Pin	Notes
MGT_CLK0_P	225	B2B, JM3-33	MGTREFCLK0P_225, Y6	Supplied by the carrier board.
MGT_CLK0_N	225	B2B, JM3-31	MGTREFCLK0N_225, Y5	Supplied by the carrier board.
MGT_CLK1_P	225	U2, CLK1B	MGTREFCLK1P_225, V6	On-board Si5338A.
MGT_CLK1_N	225	U2, CLK1A	MGTREFCLK1N_225, V5	On-board Si5338A.
MGT_CLK2_P	224	B2B, JM3-34	MGTREFCLK2P_224, AD6	Supplied by the carrier board.
MGT_CLK2_N	224	B2B, JM3-32	MGTREFCLK2N_224, AD5	Supplied by the carrier board.
MGT_CLK3_P	224	U2, CLK2B	MGTREFCLK3P_224, AB6	On-board Si5338A.
MGT_CLK3_N	224	U2, CLK2B	MGTREFCLK3N_224, AB5	On-board Si5338A.

Table x: MGT reference clock sources.

JTAG Interface

JTAG access to the ... is provided through B2B connector ....

JTAG Signal	B2B Connector Pin
TCK	JMx-xx
TDI	JMx-xx
TDO	JMx-xx
TMS	JMx-xx

Table 5: JTAG interface signals.

System Controller CPLD I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin Name	Mode	Function	B2B Connector Pin	Default Configuration
PGOOD	Output	Power Good	J1-148	Active high when all on-module power supplies are working properly.
JTAGEN	Input	JTAG Select	J2-131	Low for normal operation.
..	..	..	..	..

Table x: System Controller CPLD I/O pins.

Quad SPI Interface

Following line is just an example, change it to your needs.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Note that table column says "Signal Name", it should match the name used on the schematic.

MIO	Signal Name	U14 Pin
1	SPI-CS	C2
2	SPI-DQ0/M0	D3
3	SPI-DQ1/M1	D2
4	SPI-DQ2/M2	C4
5	SPI-DQ3/M3	D4
6	SPI-SCK/M4	B2

Table x: Quad SPI interface signals and connections.

SD Card Interface

Describe SD Card interface shortly here if the module has one...

FPGA / SoC Pin	Connected To	Signal Name
MIO0	J10-9	Card detect switch
MIO10	J10-7	DAT0
MIO11	J10-3	CMD
MIO12	J10-5	CLK
MIO13	J10-8	DAT1
MIO14	J10-1	DAT3
MIO15	J10-2	CD/DAT3

Table x: SD Card interface signals and connections.

Ethernet Interface

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

PHY Pin	PS	PL	B2B	Notes

Table x: ...

USB Interface

USB PHY is provided with ...

PHY Pin	Pin	B2B Name	Notes

Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

I2C Device	I2C Address	Notes

Table x: I²C slave device addresses.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

DDR Memory

By default TE0xxx module has ... DDRx SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

Si5338A Pin	Signal Name / Description	Connected To	Direction	Note
IN1	-	Not connected.	Input	Not used.
IN2	-	GND	Input	Not used.
IN3	Reference input clock.	U3, pin 3	Input	25.000000 MHz oscillator, Si8208AI.
IN4	-	GND	Input	I²C slave device address LSB.
IN5	-	Not connected.	Input	Not used.
IN6	-	GND	Input	Not used.
CLK0A	CLK1_P	U1, R23	Output	FPGA bank 45.
CLK0B	CLK1_N	U1, P23	Output	FPGA bank 45.
CLK1A	MGT_CLK1_N	U1, V5	Output	FPGA MGT bank 225 reference clock.
CLK1B	MGT_CLK1_P	U1, V6	Output	FPGA MGT bank 225 reference clock.
CLK2A	MGT_CLK3_N	U1, AB5	Output	FPGA MGT bank 224 reference clock.
CLK2B	MGT_CLK3_P	U1, AB6	Output	FPGA MGT bank 224 reference clock.
CLK3A	CLK0_P	U1, pin T24	Output	FPGA bank 45.
CLK3B	CLK0_N	U1, pin T25	Output	FPGA bank 45.

Table : Programmable quad PLL clock generator inputs and outputs.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Clock Source	Schematic Name	Frequency	Clock Destination
..	..	..	..
SiTime SiT8008BI oscillator, U21	-	25.000000 MHz	Quad PLL clock generator U16, pin 3.

Table : Reference clock signals.

On-board LEDs

LED	Color	Connected to	Description and Notes
D1	Green
..	..	..	..

Table : On-board LEDs.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input	Typical Current
VIN	TBD*
3.3VIN	TBD*

Table : Typical power consumption.

* TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared. <-- What?

To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

Regulator dependencies and max. current.

Put power distribution diagram here...

Figure : Module power distribution diagram.

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Put power-on diagram here...

Figure : Module power-on diagram.

Voltage Monitor Circuit

If the module has one, describe it here...

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Power Rail Name	B2B JM1 Pins	B2B JM2 Pins	Direction	Notes
VIN	1, 3, 5	2, 4, 6, 8	Input	Main supply voltage from the carrier board.
3.3V	-	10, 12, 91	Output	Module on-board 3.3V voltage supply. (would be good to add max. current allowed here if possible)
B64_VCO	9, 11	-	Input	HR (High Range) bank voltage supply from the carrier board.
VBAT_IN	79	-	Input	RTC battery supply voltage from the carrier board.
...	...	...	...	...

Table : Module power rails.

Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.

Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Bank Voltages

Bank	Schematic Name	Voltage	Voltage Range
500 (MIO0)	PS_1.8V	1.8V	-
501 (MIO1)	PS_1.8V	1.8V	-
502 (DDR3)	1.35V	1.35V	-
12 HR	VCCIO_12	User	HR: 1.2V to 3.3V
13 HR	VCCIO_13	User	HR: 1.2V to 3.3V
33 HP	VCCIO_33	User	HP: 1.2V to 1.8V
34 HP	VCCIO_34	User	HP: 1.2V to 1.8V
35 HP	VCCIO_35	User	HP: 1.2V to 1.8V

Table : Module PL I/O bank voltages.

Board to Board Connectors

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Variants Currently In Production

Trenz shop TE0xxx overview page
English page	German page

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference Document
VIN supply voltage			V	-
Storage temperature			°C	-

Table : Module absolute maximum ratings.

Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference Document
VIN supply voltage
Operating temperature

Table : Module recommended operating conditions.

Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

Date	Revision	Notes	PCN	Documentation Link
-	01	Prototypes

Table : Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

Figure : Module hardware revision number.

Document Change History

Date	Revision	Contributors	Description
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2018-07-02	v.1	Martin Rohrmüller	Initial document.

Table : Document change history.

Disclaimer

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

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02 Sept 2017

Trenz Electronic Documentation