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Table of Contents

Overview


The Trenz Electronic TE0745 is an industrial-grade module integrating a Xilinx Zynq SoC (XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.

Key Features

  • Industrial grade Xilinx Zynq SoC (XCZ7030, XC7Z035, XC7Z045)

    • Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
    • 250 FPGA PL I/Os (120 LVDS pairs possible)
    • 17 PS MIOs on B2B connector available
  • 16-bit wide 1GB DDR3L SDRAM
  • 32 MByte QSPI Flash memory
  • 4 or 8 GTX transceiver lanes (XC7Z030 variant has 4)
  • Gigabit Ethernet transceiver PHY
  • EEPROM for storing Ethernet MAC Address
  • Hi-speed USB 2.0 ULPI transceiver with full OTG support
  • Programmable quad clock generator
  • Temperature compensated RTC (real-time clock)
  • Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
  • On-board high-efficiency DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • User LED
  • Evenly-spread supply pins for good signal integrity
  • Rugged for shock and high vibration

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1TE0745-02 Block Diagram.

Main Components

Figure 2TE0745-02 SoC module.


  1. Xilinx Zynq XC7Z family SoC, U1
  2. 256 Mbit Quad SPI Flash memory Micron N25Q256A, U12
  3. Reference clock signal oscillator SiTime SiT8008BI @33.333333 MHz, U12
  4. Reference clock signal oscillator SiTime SiT8008BI @25.000000 MHz, U9
  5. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
  6. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
  7. TI TPS51206 DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
  8. Intersil ISL12020MIRZ Real-Time-Clock, U24
  9. TI TCA9517 level-shifting I2C bus repeater, U17
  10. Red LED, D2
  11. Green LED, D1
  12. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 banks a 32 MWords, 16 Bit word width), U5
  13. Altera Enpirion EN63A0QI 12A DC-DC PowerSoC @1.0V (VCCINT), U4
  14. TI TPS74401RGW LDO DC-DC regulator @1.2V (MGTAVTT), U8
  15. TI TPS72018DRVR LDO DC-DC regulator @1.8V (MGTAUX), U6
  16. TI TPS74401RGW LDO DC-DC regulator @1.0V (MGTAVCC), U11
  17. Silicon Labs Si5338A I2C Programmable Quad Clock Generator, U13
  18. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
  19. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
  20. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
  21. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
  22. 256 Mbit Quad SPI Flash memory (Micron N25Q256A), U14
  23. Microchip USB3320 USB transceiver PHY , U32
  24. Reference clock signal oscillator SiTime SiT8008BI @52.000000 MHz, U33
  25. Microchip 24AA025E48 EEPROM for MAC address, U23
  26. Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2

Initial Delivery State

Storage Device Name

Content

Notes

24AA025E48 EEPROM

User content, not programmed

Valid MAC Address from manufacturer.

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

Not programmed

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-
Si5338 OTP NVMNot programmedOTP not re-programmable after delivery from factory

Table 1: Initial delivery state.

Signals, Interfaces and Pins

Board to Board (B2B) I/O's

The B2B connectors are high-speed hermaphroditic stacking strips providing modular interface to the SoC's PL and PS I/Os. Both single ended and differential signaling LVDS pairs are supported.

BankTypeB2B ConnectorI/O Signal CountLVDS Pairs CountBank VoltageNotes
12HRJ15024VCCIO_12
pins J1-54, J1-55
Voltage range 1.2V to 3.3V
13HRJ15024VCCIO_13
pins J1-112, J1-113
Voltage range 1.2V to 3.3V
33HPJ35024VCCIO_33
pins J3-115, J3-120
Voltage range 1.2V to 1.8V
34HPJ25024VCCIO_34
pins J2-29, J2-30
Voltage range 1.2V to 1.8V
35HPJ25024VCCIO_35
pins J2-87, J2-88
Voltage range 1.2V to 1.8V
500MIOJ25-1.8VMIO0, MIO12 ... MIO15, user configurable I/O's on B2B
501MIOJ312-1.8VMIO40 ... MIO51, user configurable I/O's on B2B

Table 2: Count, type and voltage range of SoC's PL and PS I/O banks pins available through B2B connectors.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the pin-out, please refer to the Pin-out Table.

The configuration of the I/O's MIO0, MIO12 ... MIO15 and MIO40 ... MIO51 are depending on the base-board peripherals connected to these pins.

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pair, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

LaneBankTypeSignal NameB2B PinFPGA Pin
0112GTX
  • MGT_RX0_P
  • MGT_RX0_N
  • MGT_TX0_P
  • MGT_TX0_N
  • J3-50
  • J3-52
  • J3-51
  • J3-53
  • MGTHRXP0_112, AB4
  • MGTHRXN0_112, AB3
  • MGTHTXP0_112, AA2
  • MGTHTXN0_112, AA1
1112GTX
  • MGT_RX1_P
  • MGT_RX1_N
  • MGT_TX1_P
  • MGT_TX1_N
  • J3-56
  • J3-58
  • J3-57
  • J3-59
  • MGTHRXP1_112, Y4
  • MGTHRXN1_112, Y3
  • MGTHTXP1_112, W2
  • MGTHTXN1_112, W1
2112GTX
  • MGT_RX2_P
  • MGT_RX2_N
  • MGT_TX2_P
  • MGT_TX2_N
  • J3-62
  • J3-64
  • J3-63
  • J3-65
  • MGTHRXP2_112, V4
  • MGTHRXN2_112, V3
  • MGTHTXP2_112, U2
  • MGTHTXN2_112, U1
3112GTX
  • MGT_RX3_P
  • MGT_RX3_N
  • MGT_TX3_P
  • MGT_TX3_N
  • J3-68
  • J3-70
  • J3-69
  • J3-71
  • MGTHRXP3_112, T4
  • MGTHRXN3_112, T3
  • MGTHTXP3_112, R2
  • MGTHTXN3_112, R1
4111 1)GTX
  • MGT_RX4_P
  • MGT_RX4_N
  • MGT_TX4_P
  • MGT_TX4_N
  • J1-23
  • J1-21
  • J1-22
  • J1-20
  • MGTHRXP0_111, AD8
  • MGTHRXN0_111, AD7
  • MGTHTXP0_111, AF8
  • MGTHTXN0_111, AF7
5111 1)GTX
  • MGT_RX5_P
  • MGT_RX5_N
  • MGT_TX5_P
  • MGT_TX5_N
  • J1-17
  • J1-15
  • J1-16
  • J1-14
  • MGTHRXP1_111, AE6
  • MGTHRXN1_111, AE5
  • MGTHTXP1_111, AF4
  • MGTHTXN1_111, AF3
6111 1)GTX
  • MGT_RX6_P
  • MGT_RX6_N
  • MGT_TX6_P
  • MGT_TX6_N
  • J1-11
  • J1-9
  • J1-10
  • J1-8
  • MGTHRXP2_111, AC6
  • MGTHRXN2_111, AC5
  • MGTHTXP2_111, AE2
  • MGTHTXN2_111, AE1
7111 1)GTX
  • MGT_RX7_P
  • MGT_RX7_N
  • MGT_TX7_P
  • MGT_TX7_N
  • J1-5
  • J1-3
  • J1-4
  • J1-2
  • MGTHRXP3_111, AD4
  • MGTHRXN3_111, AD3
  • MGTHTXP3_111, AC2
  • MGTHTXN3_111, AC1

Table 3: SoC's MGT lanes connections to the B2B connectors.

Below are listed MGT banks reference clock sources.

Clock signalBankSourceFPGA PinNotes
MGT_CLK0_P112B2B, J3-75MGTREFCLK0P_112, R6Supplied by the carrier board.
MGT_CLK0_N112B2B, J3-77MGTREFCLK0N_112, R5Supplied by the carrier board.
MGT_CLK1_P112U16, CLK0AMGTREFCLK1P_112, U6On-module Si5338A.
MGT_CLK1_N112U16, CLK0BMGTREFCLK1N_112, U5On-module Si5338A.
MGT_CLK2_P111 1)B2B, J3-81MGTREFCLK0P_111, W6Supplied by the carrier board.
MGT_CLK2_N111 1)B2B, J3-83MGTREFCLK0N_111, W5Supplied by the carrier board.
MGT_CLK3_P111 1)U16, CLK3AMGTREFCLK1P_111, AA6On-module Si5338A.
MGT_CLK3_N111 1)U16, CLK3BMGTREFCLK1N_111, AA5On-module Si5338A.

Table 4: MGT reference clock sources.

1) Note: MGT bank 111 not available at XC7Z030 Zynq SoC.

JTAG Interface

JTAG interface access is provided through the SoC's PS configuration bank 0 and is available on B2B connector J1.

JTAG SignalB2B Connector Pin
TCKJ1-143
TDIJ1-142
TDOJ1-145
TMSJ1-144

Table 5: JTAG interface signals.

JTAG_EN pin 148 in B2B connector J1 should be kept low or grounded for normal operation!

System Controller I/O's

Following special purpose pins are connected to System Controller CPLD:

Pin NameModeFunctionB2B Connector PinDefault Configuration
JTAG_ENInputJTAG selectJ1-148

During normal operating mode the JTAG_EN pin should be in the low state for JTAG signals to be forwarded to the Zynq SoC.
If JTAG_EN pin is set to high or left open the JTAG signals are forwarded to the System Controller CPLD.

RST_IN_NInputResetJ2-131Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq chip.
PS_SRSTInputResetJ2-152Low-active PS system-reset pin of Zynq chip.
BOOTMODEOutputBoot modeJ2-133

Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133)
the boot source of the Zynq chip. See section "Boot Modes".

Permanent logic high in standard SC-CPLD firmware.

PWR_PL_OKInputPower goodJ2-135Indicates stable state of PL supply voltage (low-active) after power-up sequence.
PWR_PS_OKInputPower goodJ2-139Indicates stable state of PS supply voltage (low-active) after power-up sequence.
EN_PLOutputEnable signal-

Low active Enable-signal for activating PL supply voltage.

Permanent logic high in standard SC-CPLD firmware.

MIO8InputPS MIO-User I/O (pulled-up to PS_1.8V).
MIO0InputPS MIOJ2-137User I/O.
RTC_INTInputInterrupt signal-Interrupt-signal from on-board RTC.
LEDOutputLED control-Green LED D1, indicates SC-CPLD activity by blinking.

Table 6: System Controller CPLD special purpose I/O pins.

Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

MIOSignal NameU14 Pin
1SPI-CSC2
2SPI-DQ0/M0D3
3SPI-DQ1/M1D2
4SPI-DQ2/M2C4
5SPI-DQ3/M3D4
6SPI-SCK/M4B2

Table 7: MIO-pin assignment of the Quad SPI Flash memory IC.

Gigabit Ethernet Interface

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.

PHY PinZYNQ PSB2BNotes
MDC/MDIOMIO52, MIO53--
PHY LEDs-

PHY_LED0: J2-144
PHY_LED1: J2-146

-
PHY_LED2 / INTn:-J2-148Active low interrupt line.
PHY_CLK125M-J2-150125 MHz Ethernet PHY clock out.
CONFIG--Permanent logic high.
RESETnMIO9-Active low reset line.
RGMIIMIO16 ... MIO27-Reduced Gigabit Media Independent Interface.
SGMII--Serial Gigabit Media Independent Interface.
MDI-PHY_MDI0: J2-120 / J2-122
PHY_MDI1: J2-126 / J2-128
PHY_MDI2: J2-132 / J2-134
PHY_MDI3: J2-138 / J2-140
Media Dependent Interface.

Table 8: Ethernet PHY interface connections.

USB Interface

USB PHY (U32) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

PHY PinZYNQ PSB2BNotes
ULPIMIO28 ... MIO39-Zynq USB0 MIO pins are connected to the PHY.
REFCLK--52MHz from on board oscillator (U33).
REFSEL[0..2]--All pins set to GND selects the external reference clock frequency (52.000000 MHz).
RESETBMIO7-Low active USB PHY Reset (pulled-up to PS_1.8V).
CLKOUTMIO36-Set to logic high to select reference clock (oscillator U33) operation mode.
DP, DM-OTG_D_P, OTG_D_N,
pin J2-149 / J2-151
USB data lines.
CPEN-VBUS_V_EN,
pin J2-141
External USB power switch active-high enable signal.
VBUS-USB_VBUS,
pin J2-145
Connect to USB VBUS via a series of resistors, see reference schematics.
ID-OTG_ID,
pin J2-143
For an A-device connect to the ground. For a B-device, leave floating.

Table 9: USB PHY interface connections.

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

The I2C interface on B2B connector J2 has PS_3.3V as reference voltage and is connected to the Zynq SoC via voltage level translating (3.3V ↔ 1.8V) I2C bus repeater (U17).:

B2B pinSignal Schematic NameNotes
J2-119I2C_33_SCL3.3V reference voltage
J2-121I2C_33_SDA3.3V reference voltage

Table 10: Pin assignment of the B2B I2C interface.

The on-module I2C interface works with reference voltage 1.8V:

PS Bank 500Signal Schematic NameNotes
MIO 10I2C_SCL1.8V reference voltage
MIO 11I2C_SDA1.8V reference voltage

Table 11: MIO-pin assignment of the on-module I2C interface.

Except the on-module RTC (U24), all other on-module I2C slave devices are operating with the reference voltage PS_1.8V.

I2C addresses for on-module devices are listed in the table below:

I2C Device I2C AddressNotes
Zynq chip U1, bank 500 (PS MIO), pins MIO10 (SCL), MIO11 (SDA)User programmable.Configured as I2C by default.
Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA)0x70-
MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA)0x53-
SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL)User programmable.-
RTC, U240x6F-
RTC RAM, U240x57-

Table 12:  Module's I2C-interfaces overview.

Boot Process

TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21 (permanent logic high in standard SC-CPLD firmware).The boot mode selection will be set by the Zynq's PS MIO pins MIO3...MIO5.

Following table describes how to set the control lines to configure the boot mode:

Boot ModeMIO5 (BOOTMODE_1), SC CPLDMIO4 (BOOTMODE), J2-133Note

JTAG

00-
QSPI Flash Memory10standard mode in current configuration.
SD-Card11SD-Card on base board necessary.

Table 13: Selectable boot modes.

In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. Basically MIO5 is set to 1 and JTAG is in cascade.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I2C programmable quad PLL clock generator Si5338A (U16) on-board. It's output frequencies can be programmed by using the I2C-bus with address 0x70.

A 25 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I2C-bus connected between the Zynq module (master) and reference clock signal generator (slave).

Si5338A Pin
Signal Name / Description
Connected ToDirectionNote

IN1

CLKIN_P

B2B, J3-76Input

Reference input clock from base board.

IN2CLKIN_NB2B, J3-74Input

IN3

Reference input clock.

Oscillator U21, pin 3Input25.000000 MHz oscillator, Si8008BI.

IN4

-GNDInputI2C slave device address LSB (0x70 default address).

IN5

-

Not connected.InputNot used.
IN6-GNDInputNot used.

CLK0A

MGT_CLK1_P

Zynq Soc U1, pin U6Output

MGT bank 112 reference clock.

CLK0BMGT_CLK1_NZynq Soc U1, pin U5Output
CLK1ACLK1_PB2B, J3-80OutputReference clock output to base board.
CLK1BCLK1_NB2B, J3-82Output
CLK2ACLK2_PB2B, J3-86OutputReference clock output to base board.
CLK2BCLK2_PB2B, J3-88Output
CLK3A

MGT_CLK3_P

Zynq Soc U1, pin AA6OutputMGT bank 111 reference clock.
CLK3BMGT_CLK3_NZynq Soc U1, pin AA6Output

Table 14: Programmable quad PLL clock generator inputs and outputs.

Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Clock SourceSchematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U21-25.000000 MHzQuad PLL clock generator U16, pin 3

SiTime SiT8008BI oscillator, U12

PS_CLK33.333333 MHzBank 500 (MIO0 bank), pin B24
SiTime SiT8008BI oscillator, U33OTG-RCLK52.000000 MHzUSB 2.0 transceiver PHY U32, pin 26
SiTime SiT8008BI oscillator, U9ETH_CLKIN25.000000 MHzGigabit Ethernet PHY U7, pin 34

Table 15: Clock sources overview.

On-board LEDs

LEDColorConnected toDescription and Notes

D1

Green

System Controller CPLD, bank 3, pin 5System main status LED, blinking indicates system activity

D2

Red

Zynq chip (U1), bank 0 (config bank), 'DONE' (pin W9)

Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.

This LED remains OFF if System Controller CPLD can not power up the PL supply voltage.

Table 16: LEDs of the module.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input PinTypical Current
PL_VINTBD*
PS_VINTBD*
PS_3.3VTBD*

Table 17: Typical power consumption. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.

It is important that all baseboard I/Os are tri-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.

Power Distribution Dependencies

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC converters, which power up further DCDC converters and the particular on-board voltages:

Figure 3: Power Distribution Diagram

See Xilinx data sheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0745 module.

Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).

Power-On Sequence Diagram

The TE0745 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Figure 4: Power-On Sequence

The Enable-Signal 'EN_PL' is permanently logic high in standard SC-CPLD firmware. The "Power Good"-signals 'PWR_PS_OK' and 'PWR_PL_OK' (latter low-active, extern pull-up needed) are available B2B-connector J2 (pins J2-139, J2-135) and on the SC-CPLD.

Voltage Monitor Circuit

The voltages 'VCCPINT' and 'PS_1.8V' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (available on J2-131 or SC-CPLD) to GND. Leave this pin unconnected or connect to VDD (PS_1.8V) when unused.


Figure 5: Voltage monitor circuit.

Power Rails

Voltages on B2B
Connectors

B2B J1 Pin

B2B J2 Pin

B2B J3 Pin

Input/
Output

Note
PL_VIN

147, 149, 151, 153,
155, 157, 159

--Inputmodule supply voltage
PS_VIN-154, 156, 158-Inputmodule supply voltage
PS_3.3V-160-Inputmodule supply voltage
VCCIO1254, 55--Inputhigh range bank I/O voltage
VCCIO13112, 113--Inputhigh range bank I/O voltage
VCCIO33--115, 120Inputhigh performance bank I/O voltage
VCCIO3429, 30
-Inputhigh performance bank I/O voltage
VCCIO3587, 88
-Inputhigh performance bank I/O voltage
VBAT_IN146--InputRTC (battery-backed) supply voltage
PS_1.8V-130-Outputinternal 1.8V voltage level (Process System)

Table 18: Power rails of the SoC module on B2B connectors.

Bank Voltages

Bank

Schematic Name

Voltage

Voltage Range

0 (config)VCCIO_0

PL_1.8V, if R67 is equipped
PS_1.8V, if R68 is equipped

-
500 (MIO0)PS_1.8V 1.8V-
501 (MIO1)PS_1.8V1.8V-
502 (DDR3)1.35V1.35V-
12 HRVCCIO_12UserHR: 1.2V to 3.3V
13 HRVCCIO_13UserHR: 1.2V to 3.3V
33 HPVCCIO_33UserHP: 1.2V to 1.8V
34 HPVCCIO_34UserHP: 1.2V to 1.8V
35 HPVCCIO_35UserHP: 1.2V to 1.8V

Table 19: Range of SoC module's bank voltages.

B2B connectors

5.2 x 7.6 cm SoM Kintex modules use three Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.
  • 3x REF-192552-02 (160-pins)
    • ST5 Mates with SS5

5.2 x 7.6 cm SoM Kintex carrier use three Samtec Razor Beam LP Socket Strip (SS5) on the top side.

  • 3x REF192552-01 (160-pins)
    • SS5 Mates with ST5

Variants Currently In Production

 Module VariantZynq SoC

SoC Junction Temperature

Operating Temperature Range
TE0745-02-30-1IXC7Z030-1FBG676I–40°C to +100°CIndustrial
TE0745-02-35-1CXC7Z035-1FBG676C0°C to +85°CCommercial
TE0745-02-45-1CXC7Z045-1FBG676C0°C to +85°CCommercial
TE0745-02-45-2IXC7Z045-2FBG676I–40°C to +100°CIndustrial

Table 20: Module variants.

Technical Specification

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

PL_VIN-0.35VTI TPS720 data sheet
PS_VIN-0.37VTI TPS82085 data sheet
PS_3.3V3.1353.465V

3.3V nominal ± 5%

Attention: PS_3.3V is directly connected to numerous
on-board peripherals as supply and I/O voltage.

VBAT supply voltage-16.0VISL12020MIRZ data sheet
PL IO bank supply voltage for HR I/O banks (VCCO)-0.53.6V-

PL IO bank supply voltage for HP I/O banks (VCCO)

-0.52.0V-
I/O input voltage for HR I/O banks-0.4VCCO_X+0.55V-
I/O input voltage for HP I/O banks-0.55VCCO_X+0.55V-
GT receiver (RXP/RXN) and transmitter (TXP/TXN)-0.51.26V-

Voltage on module JTAG pins

-0.33.6

V

MachX02 Family data sheet

Storage temperature

-40

+85

°C

Limits of ISL12020MIRZ RTC chp.
Storage temperature without the ISL12020MIRZ-55+100°CLimits of DDR3 memory chips.

Table 21: Module absolute maximum ratings.

Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitsNotesReference Document
PL_VIN3.34.5V-TI TPS720 data sheet
PS_VIN3.36.0V-TI TPS82085 data sheet
PS_3.3V3.1353.465V-3.3V nominal ± 5%
VBAT_IN supply voltage2.75.5V-ISL12020MIRZ data sheet

PL I/O bank supply voltage for HR
I/O banks (VCCO)

1.143.465V-Xilinx datasheet DS191

PL I/O bank supply voltage for HP
I/O banks (VCCO)

1.141.89V-Xilinx datasheet DS191
I/O input voltage for HR I/O banks-0.20VCCO_X+0.20V-

Xilinx datasheet DS191

I/O input voltage for HP I/O banks-0.20VCCO_X+0.20V

-

Xilinx datasheet DS191
GT receiver (RXP/RXN) and transmitter (TXP/TXN)(*)(*)V(*) Check datasheetXilinx datasheet DS191
Voltage on Module JTAG pins3.1353.6VJTAG signals forwarded to
Zynq module config bank 0
MachX02 Family Data Sheet

Table 22: Module recommended operating conditions.

Please check Xilinx datasheet DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 4mm

  • PCB thickness: 1.6mm

  • Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

          

Figure 6: Physical dimensions of the TE0745 SoC module.

Revision History

Hardware Revision History

 DateRevision

Notes

Link to PCNDocumentation Link
2016-10-1102
  • First Production release
  • Refer to Changes list in Schematic for
    further details in changes to REV01

 -TE0745-02
2016-04-1801
  • Prototypes
 -TE0745-01

Table 23: Module hardware revision history.

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Figure 7: TE0745 module revision number.

Document Change History 

 Date

Revision

ContributorsDescription

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John Hartfiel
  • correction PDF link

v.80John Hartfiel
  • Update B2B Section
2017-11-13
 V.79
Ali Naseri, Jan Kumann, John Hartfiel
  • First TRM release

Table 24: Document change history.

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Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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