UM-TE0320

Figure 2: TE0320, top view.
Figure 1: TE0320, bottom view.Overview
The TE0320 is an industrial-grade FPGA micromodule integrating a leading-edge Xilinx Spartan-3A DSP FPGA, a USB 2.0 microcontroller, 32-bit wide 128 MByte DDR RAM, 4 MByte Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.
All this on a tiny footprint, smaller than a credit card, at the most competitive price. Hardware and software development environment as well as reference designs are available at: www.trenz-electronic.de.
Sample Applications
Cryptographic hardware module
Digital signal processing
Embedded educational platform
Embedded industrial OEM platform
Embedded system design
Emulation platforms
FPGA graphics
Image processing
IP (intellectual property) cores
Low-power design
Parallel processing
Rapid prototyping
Reconfigurable computing
System-on-Chip (SoC) development
Key Features
Industrial-grade Xilinx Spartan-3A DSP FPGA module (1800 k gates or 3400 k gates)
USB 2.0 (Hi-Speed USB) interface with a signalling bit rate of up to 480 Mbit/s
32-bit wide 1 Gbit DDR SDRAM
FPGA configuration through:
JTAG (B2B connector, pin header)
SPI Flash memory
Large SPI Flash memory (for configuration and operation) accessible through:
B2B connector (SPI direct)
FPGA
JTAG port (SPI indirect)
USB bus (Firmware Upgrade Tool)
On-board 100 MHz oscillator for high performance
On-board 24 MHz oscillator available to user
3 on-board high-power, high-efficiency, switch-mode DC-DC converters capable of 3 A each
Power supply range: 4.0 - 7.0 V
Power supply via USB or B2B (carrier board)
4 LEDs, 2 push buttons, 8 DIP switches.
Plug-on module with 2 female 1.27 mm pitch header connectors
109 FPGA I/O pins (+ 10 dual-purpose pins) available on B2B connectors
Evenly spread supply pins for good signal integrity
Assembly options for cost or performance optimization available on request

Table of Contents
1 Block Diagram6
2 Module options6
3 Specifications7
4 Board Dimensions8
5 Power Supply9
5.1 Power Supply Range9
5.2 Power Supply Sources9
5.3 On-Board Power Rails10
5.4 Power Supervision13
5.4.1 Power-on Reset13
5.4.2 Power Fail14
6 Inputs and Outputs15
6.1 Board-to-Board Connectors15
6.2 USB Interface17
6.2.1 USB Connector17
6.2.2 USB Pins18
6.3 JTAG Interface19
6.3.1 JTAG connector J219
6.3.2 JTAG lines at B2B connector JM421
6.4 I2C bus21
6.5 SPI bus22
6.5.1 SPI bus for configuration23
6.5.2 SPI bus for operation24
6.6 LEDs24
6.6.1 System LED D124
6.6.2 User LEDs D[5:8]25
6.7 Push-Buttons S[3:4]25
6.8 Switches26
6.8.1 DIP Slide Switches S1[A]26
6.8.2 Slide Switch S227
6.8.3 DIP Slide Switches S5[A:H]29
6.9 Voltage Reference VREF030
7 Timing31
7.1 Main Clock Oscillator31
7.2 24 MHz Clock Oscillator31
7.3 Interface Clock (IFCLK)31
7.4 Digital Clock Manager (DCM)31
7.5 Watchdog31
8 Memories34
8.1 DDR SDRAM34
8.2 SPI Flash34
8.3 Serial EEPROM34
9 System Requirements35
9.1 Power Supply Requirements35
9.2 Hardware Design Requirements35
9.3 USB Requirements35
9.4 JTAG Requirements35
9.4.1 Software Requirements35
9.5 Operating System Support36
10 Configuration37
10.1 Mode Select Pins M[2:0]38
10.2 Configuration via USB bus39
10.2.1 Cypress USB Generic Device Driver installation: it is used in case of Recovery Procedure40
10.2.2 USB FX2 microcontroller large EEPROM programming: Recovery Procedure42
10.2.3 Specific USB device driver installation: 2nd and 3rd generation45
10.2.4 Differences in files and instruments required to program USB FX2 microcontroller and/or SPI Flash for 2nd and 3rd generation firmware49
10.2.5 bitstream file from your Xilinx EDK design49
10.2.6 PROM file from the bitstream file (XILINX Flash .mcs example)49
10.2.7 Firmware Upgrade Tools utilization (OpenFutNET example)54
10.2.8 FPGA Configuration Using Upgrade Tools (OpenFutNET example for 3rd Generation Firmware, it is also possible to use Python OpenFut)58
10.3 FPGA Configuration Using Indirect SPI Configuration Mode60
11 Recommended Design Tools Settings62
11.1 DONE LED62
11.2 Unused IOB Pins63
11.3 CCLK Frequency63
12 Reference Design Summaries (ISE 11.5)64
12.1 Reference Design Summary for Xilinx Spartan-3A DSP 180064
12.2 Reference Design Summary for Xilinx Spartan-3A DSP 340066
13 Verification68
14 High Resolution Pictures70
14.1 Top View71
14.2 Bottom View72
14.3 Angle View73
15 Ordering Information74
15.1 Product Identification System74
15.2 Assembly Options Overview74
15.3 Availability75
16 Product Support76
17 Related Materials and References77
17.1 Data Sheets77
17.2 User Guides77
17.3 Tutorials77
17.4 Application Notes77
18 B2B Connectors Pin Descriptions79
18.1 Pin Labelling79
18.2 Pin Types79
18.3 B2B Connectors Pin-Out81
18.3.1 JM4 Pin-Out81
18.3.2 JM5 Pin-Out82
18.4 Signal Integrity Considerations83
18.4.1 JM4 Signals Trace Length84
18.4.2 JM5 Signals Trace Length85
19 Glossary of Abbreviations and Acronyms86
20 Legal Notices87
20.1 Document Warranty87
20.2 Limitation of Liability87
20.3 Copyright Notice87
20.4 Technology Licenses87
21 Document Change History88