The Trenz Electronic TE0865-01-DGE43FA is a high-performance MPSoC module integrating a Xilinx Zynq UltraScale+ ZU17EG (other assembly options for the FPGA are available), 8 GByte DDR4 SDRAM with ECC on PS, 8 GByte DDR4 SDRAM on PL, 256 MByte Flash memory for configuration and operation, Gigabit Ethernet PHY, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.
The prototype configuration of TE0865 will be available for approximately 3.300,- Euros, but there are still many configuration options available that you can customize to meet your specific needs.
All parts are at least extended temperature range of 0°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Refer to http://trenz.org/te0865-info for the current online version of this manual and other available documentation.
Key Features
SoC/FPGA
Package: C1760
Device: ZU11, ZU17, ZU19*
Engine: EG*
Speed: -1, -2,*, **
Temperature: I, E,*, **
RAM/Storage
Low Power DDR4 on PS
Data width: 16bit
Size: def. 2GB*
Speed: 3200 (MT/s) ***
Low Power DDR4 on PL
Data width: 16bit
Size: def. 2GB*
Speed:***
eMMC
Data width: 8Bit
size: def. 8GB *
Dual QSPI boot Flash in dual parallel mode (size depends on assembly version)
Data width: 8bit
size: def. 64MB *
MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
Initial delivery state of programmable devices on the module
Configuration Signals
Function
Schematic
Connected to
Direction
Description
Boot Mode
MODE0...3
B2B, J3A
Input
Reset
PERST0
B2B, J1B
Input
PGOOD
PG_VCCINT
CPLD, U46
Output
Power Enable
EN_VCCINT
CPLD, U46
Input
Controller signal.
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
Bank
Type
B2B Connector
I/O Signal Count
Voltage
Notes
64
HP
JM2
48x Single Ended, 24x LVDS Pairs
Variable
Max voltage 1.8V
64
HP
JM2
2x Single Ended
Variable
Max voltage 1.8V
65
HP
JM2
18x Single Ended, 9x LVDS Pairs
Variable
Max voltage 1.8V
65
HP
JM3
16x Single Ended, 8x LVDS Pairs
Variable
Max voltage 1.8V
66
HP
JM1
48x Single Ended, 24x LVDS Pairs
Variable
Max voltage 1.8V
500
MIO
JM1
8x Single Ended
1.8V
501
MIO
JM1
6x Single Ended
3.3V
505
GTR
JM3
16x Single Ended, 8x LVDS Pairs
-
4x Lanes
505
GTR CLK
JM3
1x differential Clock
-
General PL I/O to B2B connectors information
For detailed information about the pin-out, please refer to the Pin-out table.
MGT Lanes
The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Lane
Bank
Signal Name
B2B Pin
Note
0
505
B505_RX0_P
B505_RX0_N
B505_TX0_P
B505_TX0_N
JM3-26
JM3-28
JM3-25
JM3-27
1
505
B505_RX1_P
B505_RX1_N
B505_TX1_P
B505_TX1_N
JM3-20
JM3-22
JM3-19
JM3-21
2
505
B505_RX2_P
B505_RX2_N
B505_TX2_P
B505_TX2_N
JM3-14
JM3-16
JM3-13
JM3-15
3
505
B505_RX3_P
B505_RX3_N
B505_TX3_P
B505_TX3_N
JM3-8
JM3-10
JM3-7
JM3-9
MGT Lanes connection
There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.
Clock signal
Bank
Connected to
Notes
B505_CLK0_P
505
B2B, JM3-31
Supplied by the carrier board
B505_CLK0_N
505
B2B, JM3-33
Supplied by the carrier board
B505_CLK1_P
505
U10, CLK2A
On-board Si5338A
B505_CLK1_N
505
U10, CLK2B
On-board Si5338A
B505_CLK2_P
505
N/A
Not connected
B505_CLK2_N
505
N/A
Not connected
B505_CLK3_P
505
U10, CLK1A
On-board Si5338A
B505_CLK3_N
505
U10, CLK1B
On-board Si5338A
MGT Clock Sources Information
JTAG Interface
JTAG access to the UltraScale+ MPsoC FPGA through B2B connector J3B.
JTAG Signal
B2B Connector
TMS
J3B- D59
TDI
J3B- D57
TDO
J3B- D58
TCK
J3B- D56
JTAG pins connection
JTAG access to the system controller CPLD, Intel MAX10 FPGA(U46) through B2B connector J2B.
The TE0865 is equipped with an Intel MAX 10 as System Controller CPLD (U46). Please check further information in the TE0865 CPLD page.
Bank
Schematic
Connectced to
Notes
Bank 1A
VCCIO1A
3.3V
Bank 1B
TCK_MAX10
B2B, J2B
TMS_MAX10
B2B, J2B
TDO_MAX10
B2B, J2B
TDI_MAX10
B2B, J2B
VCCIO1B
3.3V
Bank 2
EN_VTT_DDR_PL
Regulator, U26
EN_+2.5V_PL_DDR
Regulator, U22
Enable Power DDR4 PL
EN_+1.2V_PL_DDR
Regulator, U24
Enable Power DDR4 PL
PG_+1.2V_PL_DDR
Regulator, U24
Power Good DDR4 PL
EN_+1.8V_AUX_PS
Regulator, U43
SC_EXT_1...4
B2B, J2B
PG_VCCINT
Regulator, U20
Configurable Regulator
LTM_FAULT
Regulator, U20
Configurable Regulator
M_SDA
I2C Bus
B2B, J2A via level shifter (U12)
M_SCL
I2C Bus
B2B, J2A via level shifter (U12)
MR
B2B, J2B
Regulator, U51
Bank 3
SMB_ALERTn
Regulator, U20
Configurable Regulator
PG_+2.5V_PL_DDR
Regulator, U22
Power Good DDR4 PL
LTM_RUNP_EN
Regulator, U20
Configurable Regulator
M_SDA
I2C Bus
B2B, J2A via level shifter (U12)
M_SCL
I2C Bus
B2B, J2A via level shifter (U12)
RST_SYSn
Diod, U53B
Reset
EN_+0.9V_GTH_AVCC
Regulator, U35
EN_+0.9V_GTY_AVCC
Regulator, U38
PG_+1.2V_PS_DDR
Regulator, U25
Power Good DDR4 PS
PG_+0.9V_GTH_AVCC
Regulator, U35
PG_+0.9V_GTY_AVCC
Regulator, U38
EN_+3.3V_SW
Regulator, U52
Secondary Power
EN_+1.2V_PLL_PS
Regulator, U42
PG_+1.8V_GTR_AVTT_PS
Regulator, U47
PG_+1.8V
Regulator, U41
EN_+2.5V_PS_DDR
Regulator, U23
Enable Power DDR4 PS
PG_+1.2V_GTY_AVTT
Regulator, U39
EN_+1.2V_GTY_AVTT
Regulator, U39
M_INT
B2B, J2A
EN_+1.8V_VCCADC
Regulator, U49
PG_+0.85V_GTR_AVCC_PS
Regulator, U48
EN_VTT_DDR_PS
Regulator, U27
EN_+1.8V
Regulator, U41
EN_+1.8V_GTY_AUX
Regulator, U40
PG_+2.3V
Regulator, U45
Bank 6
VCCIO6
3.3V
Bank 5
EN_+1.8V_GTR_AVTT_PS
Regulator, U47
EN_+1.8V_GTH_AUX
Regulator, U37
EN_+1.8V_AUX
Regulator, U50
EN_+1.2V_GTH_AVTT
Regulator, 36
PG_+1.2V_GTH_AVTT
regulator, U36
+3.3V_SW
eMMC, U1
EN_+1.2V_PS_DDR
Regulator, U25
Power Good DDR4 PS
EN_+0.85V_GTR_AVCC_PS
Regulator, U48
PG_+1.2V_GTH_AVTT
Regulator, U48
EN_VCCINT
Regulator, U20
EN_+2.3V
Regulator, U45
PG_+1.8V_AUX
Regulator, U50
PG_+2.5V_PS_DDR
Regulator, U23
Power Good DDR4 PS
CPLD pin connections
Dual QSPI Flash Memory
The TE0865 is equipped with dual 128 Mb (256 Mb) QSPI flash memory, U32 and U33 for configuration and operation storage.
Designator
Pin
Schematic
Notes
U32
CLK
MIO0
DI/IO0
MIO4
DO/IO1
MIO1
nWP/IO2
MIO2
nHOLD/IO3
MIO3
nCS
MIO5
U33
CLK
MIO12
DI/IO0
MIO8
DO/IO1
MIO9
nWP/IO2
MIO10
nHOLD/IO3
MIO11
nCS
MIO7
Quad SPI interface MIOs and pins
eMMC Memory
The TE0865 is equipped with an eMMC Flash memory IC(U1) connected to the PS MIO pins MIO13..MIO22. The eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.
Designator
Pin
Schematic
Connected to
Notes
U32
CLK
MMC-CCLK
MIO22
nRESET
RST_PERn
-
PS_RSTn, PS_SYSn
CMD
MMC-CMD
MIO21
DAT0...7
MMCD0...7
MIO13...20
eMMC connections
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U17) is provided with Marvell Alaska 88E1512 IC (U17). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the ETH is supplied from an on-board 25.00 MHz oscillator (U18).
Pin
Schematic
Connected to
Note
MDIP0...3
PHY_MDI0...3
B2B, J3A
MDC
ETH_MDC
MIO76
MDIO
ETH_MDIO
MIO77
S_IN
S_IN
N.C
S_OUT
S_OUT
N.C
TXD0..3
ETH_TXD0...3
MIO65...68
TX_CTRL
ETH_TXCTL
MIO69
TX_CLK
ETH_TXCK
MIO64
RXD0...3
ETH_RXD0...3
MIO71...74
RX_CTRL
ETH_RXCTL
MIO75
RX_CLK
ETH_RXCK
MIO70
LED1
PHY_LED1
B2B, J3A
RESETn
ETH_RST
MIO24
XTAL_IN
ETH_CLK
Oscillator, U18
Input Clock of ETH Transciever
nRESET
RST_PERn
B2B, J2A
PS_RSTn, PS_SYSn
GigaBit Ethernet connection
USB2.0 Transceiver
Hi-speed USB2.0 transceiver (U2) is provided with USB3340 from Microchip. The transceiver is connected to the PS MIO via MIO52..63. The I/O voltage is fixed at 3.3V (VBAT) and PHY reference clock input is supplied from the on-board 24.00 MHz oscillator (U13).
Pin
Schematic
MIO
B2B Name
Notes
RESETB
RST_PERn
RST_PERn
VBAT
VBAT
3.3V
CPEN
USB_CPEN
B2B, J3A
VBUS
USB_VBUS
B2B, J3A
ID
USB_ID
B2B, J3A
DP, DM
USB_DP
USB_ DM
B2B, J3A
REFCLK
USB_CLK24_PHY
-
-
24.00MHz from on-board oscillator (U13).
REFSEL[0..2]
-
-
-
Reference clock frequency select, all set to 1.8V selects 24 MHz.
DATA0...7
USB_DATA0...7
MIO 56,57,54, 59...62
-
Connected to 1.8V, selects reference clock operation mode.
STP
USB_STP
MIO58
-
USB data lines routed to B2B connector JM3 pins 47 and 49.
NXT
USB_NXT
MIO55
-
External USB power switch active high enable signal, routed to JM3 pin 17.
DI
USB_DI
MIO53
-
Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.
CLKOUT
USB_CLKOUT
MIO52
-
For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.
General overview of the USB PHY signals
EEPROM
There is an EEPROM (U14) provided on the module TE0865 for storing MAC Address. The EEPROM is in I2C Bus address of 0x53.
MIO Pin
Schematic
U25 Pin
Notes
MIO39
I2C_SDA
SDA
MIO38
I2C_SCL
SCL
I2C EEPROM interface MIOs and pins
Crypto Authentication
The TE0865 is equipped with an Authentication IC, ATECC608A (U19) includes an EEPROM array which can be used for storage of up to 16 keys, certificates, miscellaneous read/write, read-only or secret data, consumption logging, and security configurations. Access to the various sections of memory can be restricted in a variety of ways and then the configuration can be locked to prevent changes.
Pin
Schematic
Connected to
Notes
SDA
M_SDA
B2B, J2A
M_SDA_PS
SCL
M_SDA
B2B, J2A
M_SCL_PS
Crypto Authentication connection
OPTIGA Authentication
The TE0865 is equipped with an OPTIGA Trust M IC, SLS32AIA010MH (U16). The OPTIGA Trust M comes with up to 10kB of user memory that can be used to store X.509 certificates and data. OPTIGA Trust M is based on Common Criteria (CC) Certified EAL6+ (high) hardware enabling it to prevent physical attacks on the device itself and providing high assurance that the keys or arbitrary data stored cannot be accessed by an unauthorized entity. The OPTIGA Trust M is connected via I2C with address of 0x30.
Pin
Schematic
Connected to
Notes
SDA
M_SDA
B2B, J2A
SCL
M_SDA
B2B, J2A
RST
RST_SECn
B2B, J2A
PS_RSTn
OPTIGA Authentication connection
PL DDR4 SDRAM
The TE0865 SoM has four 2GB volatile DDR4 SDRAM ICs connected to Programmable Logic(PL) for operations, storing and streaming data.
Part number: MT40A1G16RC-062E
Supply voltage: 1.2V
Speed: 3200 MT/s
Temperature: -40 ~ 95 °C
PS DDR4 SDRAM
The TE0865 SoM has five 2GB volatile DDR4 SDRAM ICs connected to Processing System (PS) for operations, storing and streaming data.
Part number: MT40A1G16RC-062E
Supply voltage: 1.2V
Speed: 3200 MT/s
Temperature: -40 ~ 95 °C
Clock Sources
Designator
Description
Frequency
Note
U3
MEMS Oscillator
27 MHz
MGT_CLK0
U4
MEMS Oscillator
100 MHz
MGT_CLK1
U13
MEMS Oscillator
24 MHz
USB_CLK
U18
MEMS Oscillator
25 MHz
ETH_CLK
U31
MEMS Oscillator
200 MHz
DDR4 Clock
U34
MEMS Oscillator
33.33 MHz
PS REF CLK
Osillators
Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 3.0 A for system startup is recommended.
The LTM4700 (U20) is a dual 50A or single 100A step-down µModule(power module) DC/DC regulator featuring remote configurability and telemetry-monitoring of power management parameters over standard I2C-based digital interface protocol.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter
Min
Max
Units
Reference Document
VCCR
11.5
12.5
V
See LTM4700 (U20) datasheet.
T_OPT
0
85
°C
See components datasheet
Recommended operating conditions.
Components are mainly classified in 3 temperature groups, according to range specifications: commercial: 0°C - 75°C extended: 0°C - 85°C industrial: -40°C - 85°C
Classification of the module can be locked up here: Article Number Information i.e.: TE0803-03-5D"I"21-AS (The I indicates industrial)
The actual operation temperature range depends on the FPGA/SoC design/utilization and cooling, as well as other variables. Please note: These are only indications!
Physical Dimensions
Module size: 75 mm × 100 mm. Please download the assembly diagram for exact numbers.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Date
Revision
Contributor
Description
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The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
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Copyright Notice
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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