PS Peripherals
| MIO Pin | Mapped to | Pull up/down | Notes |
|---|---|---|---|
| 0 | |||
| 1 | QSPI0 | ||
| 2 | QSPI0 | Down | |
| 3 | QSPI0 | Down | |
| 4 | QSPI0 | Down | Override to up on base for bootmode change |
| 5 | QSPI0 | Up | |
| 6 | QSPI0 | Down | |
| 7 | GPIO | Down | On-board LED |
| 8 | CAN1 TXD | Down | CAN transceiver in SBC |
| 9 | CAN1 RXD | CAN transceiver in SBC | |
| 10 | SPI1 MOSI | ||
| 11 | SPI1 MISO | ||
| 12 | SPI1 SCLK | ||
| 13 | SPI1 SS0 | ||
| 14 | I2C0 SCL | ||
| 15 | I2C0 SDA |
PS and PL Banks
| Bank | VCCIO | B2B I/O Pins | Notes |
|---|---|---|---|
| 500 | 3.3V | 0 | |
| 501 | USER | 36 | |
| 13 | USER | 48 | Differential routing |
| 33 | 3.3V | 33 | Single ended routing |
| 34 | 3.3V | 0 | Ethernet PHY's |
| 35 | 3.3V | 42 | Single ended routing |
Overview
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