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TEM0703 with TEM0007


Overview


TEM0007 module is a Microchip Polarfire SoC  module. 

TEM0007 Module
  1. Microchip Polarfire SoC MPFS250T, U2
  2. 1 GByte LPDDR4 SDRAM, U6
  3. Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver, U7
  4. Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver, U11
  5. Lattice Semiconductor MachXO2 System Controller CPLD, U1
  6. B2B Connector Samtec Razor Beam, JM1...3
  7. EEPROM, U10
  8. Serial NOR Flash, U3


Required Hardware

HardwareQuantityNote
TEM00071Microchip Polarfire SoC Module
TEM07031

Carrier board

Modified TE0703:

  • FTDI Firmware
  • Added second uart (uart0)
  • Additional Reset push button
TE07901Universal USB2.0 to JTAG/UART
Mini USB Cable2
RJ45 Ethernet Cable1
USB Stick1Optional
Heatsink1


Hardware overview


Power supply

Supply voltageCurrentDesignatorDescription
5V2A*J13 on the carrier board

*Current is dependent on design and the used heatsink. This value is recommend value. 

DIP Switches

In this case S2 dip switches can be use for JTAG adjustment only and it will not be used to select boot mode, because TEM0007 supports only SD card boot mode.

S2-1S2-2S2-3S2-4Description
CM1CM0JTAGENMIO0
S2-2S2-3CM0JTAGENDescription
OFFOFF11Access to TE0703 CPLD
OFFON10Access to CPLD of B2B Module
ONOFF01Access to TE0703 CPLD
ONON00Access to FPGA of B2B Module

Reset

There are one reset push button on the board. Second reset button can be added on the board as optional reset.

 SignalPush buttonFPGA PinConnected toAccess on the carrier board viaDescription
RESINS1DEVRST_NCPLD of TEM0007 via B2B connector (SC_RESET / MR_n)S1This reset signal does not exist in Libero design. This reset signal resets FPGA via CPLD Firmware of TEM0007 module.
RESETNUser buttonH13JM2-Pin 73JB2-pin 74 /  J2C-C4User button does not exist on the carrier board. User button should be soldered by the user himself. (Optional) This button should be pulled up via a 10k resistor.

Boot mode

This module supports only SD card boot mode. Therefore there is no dip switch to select boot mode. But there is a jumper on the TEM0703 carrier board to select SD card voltage correctly. For this purpose set jumper J11 of the carrier board for 3.3V voltage.

Set SD card voltage


JTAG

JTAG signals

UART

There is two UART interfaces.

UARTFPGA PinConnected toAccess on the carrier board viaInterface forBaud rateDescription
UART0C2 (TXD)JM1-Pin 99JB1-Pin 100 / J2A-Pin 31 (TXD)HSS (Hardware System Service)115200

There is no connector on the TEM0703 carrier board PCB REV06. In this case user should connect these pins to USB to JTAG/UART converter same as TE0790. (Crosstalk)


D3 (RXD)JM1-Pin 97JB1-Pin 98 / J2A-Pin 30 (RXD) 
UART1H5 (TXD)JM1-Pin 85

JB1-Pin 86 /
J4 Mini USB connector

Linux console / Bare metal interface115200
H2 (RXD)JM1-Pin  92JB1-Pin 91 /
J4 Mini USB connector
RPI_UARTA7 (TXD)JM1-Pin 65JB1-Pin 66Additional UART interfaceDepends on system clock frequency.
Baud_rate = clk/(Baudval+1)*16 and  Baudval = (clk/(1+Baudrate)) - 1		This UART interface works via COREUARTapb in Libero.
H15 (RXD)JM2-Pin 66JB2-Pin 65

I2C

I2CFPGA PinConnected toAccess on the carrier board viaDescription
I2C0A3 (SCL)JM1-Pin 95 JB1-Pin 96 (SCL)
E3 (SDA)JM1-Pin 93JB1-Pin 94 (SDA) 
I2C1C1 (SCL)EEPROM chip U10 SCL pin No Access
 B1 (SDA)EEPROM chip U10 SDA pinNo Access
CORE_I2CB8 (SCL)JM1-Pin 62JB1-Pin 61This additional i2c interface in generated via COREI2C.
A8 (SDA)JM1-Pin 60JB1-Pin 59
RPI_I2CF10 (SCL)JM2-Pin 85JB2-Pin 86This additional i2c interface in generated via COREI2C.
B9 (SDA)JM1-Pin 68JB1-Pin 67


GPIOs

GPIOFPGA PinSchematic labelNew design label Connected toAccess on the carrier board viaDescription
GPIO_1_16E5ETH_RSTGPIO_1_16ETH_RSTNo AccessPhy chip reset pin  (Marvell 88E1512-A0-NNP2I000). Necessary for reset pin of ethernet phy chip
GPIO_1_17E4OTG-RSTGPIO_1_17OTG-RSTNo AccessUSB phy chip reset pin (Microchip USB3320-EZK). Necessary for reset pin of usb phy chip
GPIO_1_18B2---Not used---No Access
GPIO_1_19A2---Not used---No Access
GPIO_1_20B3GPIO1GPIO_1_20B2B JM1-Pin 91B2B JB1-Pin 92
GPIO_1_23D4GPIO0GPIO_1_23B2B JM1-Pin 87B2B JB1-Pin 88
GPIO_2_0U12B0_HSIO94_PNot used---No Access
GPIO_2_1T13B0_HSIO95_NNot used---No Access
GPIO_2_6R12B0_HSIO95_PNot used---No Access
RPi_GPIO12D9GPIO174_PGPIO_2_2JM1-Pin 69JB1-Pin 70
RPi_GPIO13D6GPIO168_NGPIO_2_3JM1-Pin 88JB1-Pin 87
RPi_GPIO16C6GPIO171_PGPIO_2_4JM1-Pin 83JB1-Pin 84
RPi_GPIO17H17GPIO8_NGPIO_2_5JM2-Pin 62JB2-Pin 61
RPi_GPIO19B5GPIO170_NGPIO_2_7JM1-Pin 70JB1-Pin 69
RPi_GPIO20C5GPIO170_PGPIO_2_8JM1-Pin 72JB1-Pin 71
RPi_GPIO21C4GPIO169_PGPIO_2_9JM1-Pin 77JB1-Pin 78
RPi_GPIO22F11GPIO181_NGPIO_2_10JM2-Pin 65JB2-Pin 66
RPi_GPIO23F16GPIO11_NGPIO_2_11JM2-Pin 41JB2-Pin 42
RPi_GPIO24D14GPIO2_NGPIO_2_12JM1-Pin 46JB1-Pin 45
RPi_GPIO25E14GPIO9_NGPIO_2_13JM2-Pin 57JB2-Pin 58
RPi_GPIO26B4GPIO169_NGPIO_2_14JM1-Pin 75JB1-Pin 76
RPi_GPIO27G17GPIO8_PGPIO_2_15JM2-Pin 64JB2-Pin 63


User IOs

InputFPGA PinSchematic labelConnected toAccess on the carrier board viaDescription
SW2U18B0_HSIO74_N---No Access
SW3W19B0_HSIO79_P---No Access
OutputFPGA PinSchematic labelConnected toAccess on the carrier board viaDescription
LED0V14B0_HSIO90_P---No Access
LED1U13B0_HSIO93_N---No Access
LED2T12B0_HSIO94_N---No Access
LED3AB19B0_HSIO70_PJM3-Pin 60JB3-Pin 59


PWM

SignalFPGA PinConnected toAccess on the carrier board viaDescription
PWME11JM1-Pin 82JB1-Pin 81 / J1C-Pin C4



























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