TEM0007 Test Board

Overview

Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.

Key Features

• Libero SoC v2023.1
• SoftConsole v2022.2-RISC-V-747
• PolarfireSoC MSS Configurator v2023.1
• HSS (Hardware System Service) v2023.02
• Microchip polarfire SoC BSP v2022.11
• Yocto Kirkstone
• UART
• ETH
• USB
• I2C
• QSPI flash
• DDR3 memory
• User LED

Revision History

Release Notes and Know Issues

Requirements

Software

Additional software requirement

Hardware

Complete List is available on <project folder>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and usage of the reference design, see Project Delivery - Microchip devices

Design Sources

Prebuilt

Download

Reference Design is only usable with the specified Libero version. Do never use different versions of Libero software for the same project.

Reference Design is available on:

• TEM0007 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Libero Design Flow.

See also:

• Project Delivery - Microchip devices

The most Trenz Electronic FPGA Reference Designs are TCL-script based projects.

The "normal" Libero project will be generated in the subfolder "/Libero/" and the additional software part will be generated in the subfolder "/software/" after executing scripts.

To create project do the following steps:

1. Execute "Generate_TEM0007_Hardware-Design_in_Libero_SoC_v2023.1.cmd"
2. Choose one of the following options::
   1. Press 0 , if the path of installed libero software is : C:/Microchip/Libero_SoC_v2023.1/Designer/bin/libero.exe 
      
   2. Press 1, if it will be entered the path  Microchip or Libero SoC installations folder. The script selects automatically the Libero exe.
   3. Press 2, if it will be entered the full path to the Libero SoC exe.
      
   4. Press 3 to exit the script.
3. Select your board in "Board selection" , if there is more than one variant.
4. Choose one of the following options for prefered hardware description language:
   1. Option 0 : VHDL
   2. Option 1 : VERILOG
   3. Option 2 :  To exit th script
5. If the suggested name for the project is acceptable enter y or t or 1. Otherwise enter n or f or 0 and enter the desired name.
6.  Project will be generated automatically.
7. Open the generated project by entering y or t or 1
   

   

   Example
8. After opening Libero project double click on Generate Bitstream menu in Design Flow box to generate the bitstream file.
   
   Generate Bitstream

   

   
   
9. After generating bit stream file double click on Configure Design Initialization Data and Memories in Design Flow bow. It will be opened a window.
   
   Configure Memory

   

10. Click on eNVM and after that on Add and click on Add Boot Mode 1 Client.
    
11. Enter the path of generated *.hex File by SoftConsole software (HSS) and click on OK.
    
    HSS generated *.hex File attachment

    

12. Save the project and double click on Generate Bitstream again.
    
    Generate Bitstream again

    

13. Double click on Flashpro Express to generate *.job File
    
    Generate Job File

    

Launch

Programming

Programming eNVM

The eNVM is a user non-volatile flash memory that can be programmed independently. There is two methods to program eNVM:

Programming eNVM in SoftConsole

To program HSS *.elf file on FPGA:

• Connect the modified TE0703 board via its Mini-USB connector. (J4)
• Open SoftConsole software as administrator, if it is not done yet.
• Select correct directory as workspace directory.
• Build the hart-software-services-master , if it is not done yet.
• Click on Run > External Tools > Polarfire SoC program non-secure boot-mode 1

Programming eNVM in Flashpro Express

The HSS generated hex file can be attached to bitstream file. For more information see #Design Flow

To program the eNVM in Flashpro Express see #Using FlashPro Express

Programming Bitstream

There is two ways to program bitstream file on FPGA:

• Using Libero SoC

  • Connect the TEM0703 board via its Mini-USB connector. (J4)
  • After generating bitstream in Libero click on  Run PROGRAM Action to program bitstream file on FPGA.
    
    Programming FPGA using Libero SoC

    

• Using FPExpress software

  • Connect the board via USB connector
  • Export  *.job file , if does not exist yet.
    
    Job File Exporting using Libero SoC

    

  • Open FPExpress software

    

    
    

  • Click on new
  • Give path of job file by clicking on Browse
  • Click on OK
  • Click on RUN

Get prebuilt boot binaries

1. Run create_project_win.cmd/create_project_linux.sh
2. Select Module in 'Board selection'
3. Click on 'Export prebuilt files' button
   1. Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened

SD-Boot mode

This module supports SD card boot mode. There is no dip switch to select boot mode. The selection between SD card or other boot mode will be done in HSS. TEM0007 module supports SD card boot mode and JTAG boot mode.

Prepare SD card as follows for SD card boot mode:

1. Extract SD_Card.zip file
2. Now there is a image file (SD_Card.img)
3. Alternative SD card can be written via Win32DiskImager or balenaEtcher softwares in Windows OS.
4. In the case of writing image file in  linux there are two commands to write image file on the SD card after mounting SD card in the host linux same as WSL:

1. 1. Insert SD card in the SD card reader
   2. bmaptool command

      bmaptool copy --nobmap <Path of image file *.img>  /dev/sdX

      
      
      1. After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.
   3. dd command

      dd if=<Path of image file *.img> of=/dev/sdX

      1. After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.

JTAG

Not used on this example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Connect your board to the network
4. Power on PCB

UART

1. Open Serial Console (e.g. PuTTY)

   1. select COM Port

      Win OS: see device manager

      Linux OS: see  dmesg | grep tty  (UART is *USB1)

   2. Speed: 115200
2. Press reset button
3. Console output depends on used Software project, see Software Design - SDK#Application
4. Linux Console:

   1. Login data:

      Note: Wait until Linux boot finished

      tem0007 login: root
      

   2. You can use Linux shell now.

      i2cdetect -y -r 1   (check I2C 1 Bus)
      dmesg | grep rtc    (RTC check)
      udhcpc              (ETH0 check)
      lsusb               (USB check)

5. ...

System Design - Libero

Block Design

The block designs may differ depending on the assembly variant.

HPS Interfaces

Activated interfaces:

Software Design - SoftConsole

Application

Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

...

HSS (Hart Software Service)

This is Hart Software Services (HSS) code.On PolarFire SoC, this is comprised of two portions:

• A superloop monitor running on the E51 minion processor, which receives requests from the individual U54 application processors to perform certain services on their behalf;

• A Machine-Mode software interrupt trap handler, which allows the E51 to send messages to the U54s, and request them to perform certain functions for it related to rebooting a U54.

The HSS performs boot and system monitoring functions for PolarFire SoC. The HSS is compressed (DEFLATE) and stored in eNVM. On power-up, a small decompressor wrapper inflates the HSS from eNVM flash to L2-Scratchpad memory and starts the HSS.

Creating HSS workspace in SoftConsole

• Download the HSS folder here: hart-software-services
• Unzip the hart-software-services-master zip file in the SoftConsole workspace
• Open SoftConsole software as administrator
• Select correct directory as workspace directory. The workspace folder must consist of hart-software-services-master folder
• Right click on board folder in the left side and click on new folder
• Rename the folder for desired board. For example for TEM0007 module rename it to TEM0007. If there is TEM0007, this HSS workspace was created already and HSS is ready to be compiled.
  
• Create other subfolders as shown (For example for TEM0007):
  
  
  HSS Structure Example

  

  • hart-software-serevices-master
    • board
      • TEM0007
        • drivers_config
          • fpga_ip
            • miv_ihc
              • Copy miv_ihc_add_mapping.h and miv_ihc_config.h files from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste in this folder.
        • fpga_design_config
          • This folder should be left empty. After compiling the neccessary header files for ddr, clock, IOs and other properties of desired module and hardware design will be generated and saved in this folder by mpfs_configuration_generator.py python script. The python script is saved already in the tools/polarfire-soc-configuration-generator folder.
            
        • mpfs_hal_config
          • Copy  mss_sw_config.h file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste
            
        • soc_fpga_design
          • xml
            • Copy the generated xml with PolarFireSoC MSS Configurator software here. For example TEM0007_MSS_mss_cfg.xml
              
        • Copy the following files from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste in this folder (TEM0007 folder) :
          • hss_board_init.c
          • hss_usrt_init.c
          • usrt_helper.c
          • hss_I2Scratch.lds
          • Kconfig
            • Edit Kconfig for example for TEM0007 module as shown:
              
              Kconfig

              Kconfig

              menu "TEM0007 Design Configuration Options"
              
              config SOC_FPGA_DESIGN_XML
              	string "Enter path to Libero XML file"
              	default "boards/$(BOARD)/soc_fpga_design/xml/TEM0007_MSS_mss_cfg.xml"
              	help
              		This option specifies the design XML file to use.
              endmenu
              
              

• • • • • • Makefile
            • Edit Makefile for example for TEM0007 module as shown:
              
              Makefile of TEM0007 folder

              

              Makefile of TEM0007 folder
  • Edit Makefile in hart-software-services-master Folder for example for TEM0007 as shown:
    
    Makefile of hart-software-services-master

    

    Makefile of hart-software-services-master folder
  • Copy def_config file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste it in hart-software-services-master folder and rename it to .config file.
    • Edit .config file according to your module. For example for TEM0007 is edited this file as shown:
      
      .config File

      

      .config File
  • Now HSS workspace is ready to be compiled. Right click on hart-software-services-master and  click on Build Project.
  • After compiling a config.h will be generated in the hart-software-services-master folder. By opening this header file it can be seen all configurations of .config file.

Software Design - Yocto

Trenz electronic has developed his own BSP for Microchip devices same as polarfire soc in Yocto. In the following will be explained the folders in detail.

In the following table exists more information about required packets and supported version.

Trenz BSP contains of a shell script. If this shell script in be executed , all required processes for making a linux image file will be executed. The user needs only to write the image file on the SD card. To prepare the image file :

1. Download and save meta-trenz-polarefile-bsp folder in the host linux
2. In meta-trenz-polarfire-bsp execute shell script via the following command:

   	. ./meta-trenz-polarfire-bsp/trenz_polarfire_setup.sh

3. Enter the machine name. Here the machine is equal to module name , but with lower case letters. For example for TEM0007 module enter : tem0007

   

4. Enter the image type. It depends on the user application and required installed packages in linux. As default the user can enter: te-image-minimal

   

5. After compiling image file *.img and its converted zip file *.zip will be in trenz bsp folder saved :

• • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.img
  • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.zip

For Yocto installation and project creation, follow instructions from:

• Yocto KICKstart
• Create a custom BSP layer for Microchip SoC or FPGA

U-Boot

Start with Create a custom BSP layer for Microchip SoC or FPGA#Configure u-boot

File location: meta-<module>/recipes-bsp/u-boot/

Changes:

• No changes

Device Tree

U-boot Device Tree

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2020 Microchip Technology Inc.
 * Padmarao Begari <padmarao.begari@microchip.com>
 */

/ {
	aliases {
		cpu1 = &cpu1;
		cpu2 = &cpu2;
		cpu3 = &cpu3;
		cpu4 = &cpu4;
	};
};

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 Microchip Technology Inc.
 * Padmarao Begari <padmarao.begari@microchip.com>
 */

/dts-v1/;

#include "microchip-mpfs.dtsi"
#include "dt-bindings/gpio/gpio.h"

/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ		1000000

/ {
	model = "Microchip PolarFire-SoC Icicle Kit";
	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";

	aliases {
		serial1 = &uart1;
		ethernet0 = &mac0;
		spi0 = &qspi;
	};

	chosen {
		stdout-path = "serial1";
	};

	cpus {
		timebase-frequency = <RTCCLK_FREQ>;
	};

	ddrc_cache: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		clocks = <&clkcfg CLK_DDRC>;
		status = "okay";
	};
   
    usb_phy: usb_phy {
        #phy-cells = <0>;
        compatible = "usb-nop-xceiv";
        reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
        reset-names = "OTG_RST";
    };    
};

&uart1 {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-mmc-highspeed;
	cap-sd-highspeed;
    cd-debounce-delay-ms;
	card-detect-delay = <200>;
	// mmc-ddr-1_8v;
	// mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&i2c1 {
	status = "okay";
    #address-cells = <1>;
	#size-cells = <0>;
	eeprom: eeprom@50 {
		compatible = "microchip,24aa025", "atmel,24c02";
        //compatible = "atmel,24c02";
		reg = <0x50>;
		#address-cells = <1>;
		#size-cells = <1>;        
		eth0_addr: eth-mac-addr@FA {
			reg = <0xFA 0x06>;
		};
	};
};

&refclk {
	clock-frequency = <125000000>;
};

&mac1 {
	status = "disabled";
};

&mac0 {
	status = "okay";
	phy-mode = "sgmii";
    nvmem-cells = <&eth0_addr>;
	nvmem-cell-names = "mac-address";
	phy-handle = <&phy0>;
	phy0: ethernet-phy@1 {
		device-type = "ethernet-phy";
		reg = <1>;       
        reset-names = "ETH_RST";
        reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};
};



&qspi {
	status = "okay";
	num-cs = <1>;
	flash0: spi-nor@0 {
		compatible = "spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <20000000>;
		spi-cpol;
		spi-cpha;
	};
};

&usb {
	status = "okay";
	dr_mode = "otg";  
	// dr_mode = "host";
	phys = <&usb_phy>;
};

Kernel Device Tree

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */

/dts-v1/;

#include "mpfs.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ		1000000

/ {
	#address-cells = <2>;
	#size-cells = <2>;

    
	model = "Trenz TEM0007";
	compatible = "trenz,tem0007","microchip,mpfs";
    
	aliases {
		ethernet0 = &mac0;
		serial0 = &mmuart0;
		serial1 = &mmuart1;
		serial2 = &mmuart2;
		serial3 = &mmuart3;
		serial4 = &mmuart4;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};

	cpus {
		timebase-frequency = <MTIMER_FREQ>;
	};



	//******************************************************//

	ddrc_cache: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		status = "okay";
	};

	reserved-memory {	
		#address-cells = <2>;
		#size-cells = <2>;

		ranges;

		fabricbuf0ddrc: buffer@A0000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xA0000000 0x0 0x2000000>;
			no-map;
		};
	};
    
	udmabuf0 {
		compatible = "ikwzm,u-dma-buf";
		device-name = "udmabuf-ddr-c0";
		minor-number = <0>;
		size = <0x0 0x2000000>;
		memory-region = <&fabricbuf0ddrc>;
		sync-mode = <3>;
	};


	//******************************************************//

	usb_phy: usb_phy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
		reset-names = "OTG_RST";
	};


	soc {
		dma-ranges = <0 0 0 0 0x40 0>;
	};
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	interrupts = <53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>;
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";    
	#address-cells = <1>;
	#size-cells = <0>;

	eeprom: eeprom@50 {
		compatible = "microchip,24aa025", "atmel,24c02";
        //compatible = "atmel,24c02";
		reg = <0x50>;
		#address-cells = <1>;
		#size-cells = <1>;        
		eth0_addr: eth-mac-addr@FA {
			reg = <0xFA 0x06>;
		};
	};
};


&mac0 {
	status = "okay";
	phy-mode = "sgmii";    
	nvmem-cells = <&eth0_addr>;
	nvmem-cell-names = "mac-address";
                                   
	phy-handle = <&phy0>;
	phy0: ethernet-phy@1 {
		device-type = "ethernet-phy";
		reg = <1>;
		reset-names = "ETH_RST";
		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};
};

&mbox {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	// mmc-ddr-1_8v;
	// mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};


&mmuart1 {
	status = "okay";
};

&mmuart2 {
	status = "okay";
};

&mmuart3 {
	status = "okay";
};

&mmuart4 {
	status = "okay";
};


&qspi {
	status = "okay";
	num-cs = <1>;
};

&refclk {
	clock-frequency = <125000000>;
};


&spi0 {
	status = "okay";
};


&usb {
	status = "okay";
	dr_mode = "otg";  
	// dr_mode = "host";
	phys = <&usb_phy>;
};

&syscontroller {
    status = "okay";
};
    

Kernel

Start with Create a custom BSP layer for Intel SoC or FPGA#Configure linux kernel

File location: meta-<module>/recipes-kernel/linux/

Changes:

• No changes.

Images

Image recipe for minimal console image

File location: meta-<module>/recipes-images/yocto/

Image recipes:

• te-image-minimal.bb: create minimal linux image
• te-initramfs.bb: required for building an image with initial RAM Filesystem

Added packages/recipes:

• No packages/recipes

Rootfs

Used filesystem: Initial RAM Filesystem (initramfs)

Appx. A: Change History and Legal Notices

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