TEM0007 Test Board

Overview

Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.

Key Features

• Libero SoC v2023.1
• SoftConsole v2022.2-RISC-V-747
• PolarfireSoC MSS Configurator v2023.1
• HSS (Hardware System Service) v2023.02
• Microchip polarfire SoC BSP v2022.11
• Yocto Kirkstone
• UART
• ETH
• USB
• I2C
• QSPI flash
• DDR3 memory
• User LED

Revision History

Release Notes and Know Issues

Requirements

Software

Additional software requirement

Hardware

Complete List is available on <project folder>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and usage of the reference design, see Project Delivery - Microchip devices

Design Sources

Prebuilt

Download

Reference Design is only usable with the specified Libero version. Do never use different versions of Libero software for the same project.

Reference design is available on:

• TEM0007 "Test Board" Reference Design

Design Flow

Hart Software Services (HSS)

This is Hart Software Services (HSS) code.On PolarFire SoC, this is comprised of two portions:

• A superloop monitor running on the E51 minion processor, which receives requests from the individual U54 application processors to perform certain services on their behalf;

• A Machine-Mode software interrupt trap handler, which allows the E51 to send messages to the U54s, and request them to perform certain functions for it related to rebooting a U54.

The HSS performs boot and system monitoring functions for PolarFire SoC. The HSS is compressed (DEFLATE) and stored in eNVM. On power-up, a small decompressor wrapper inflates the HSS from eNVM flash to L2-Scratchpad memory and starts the HSS.

Creating HSS workspace in SoftConsole

1. Download the test board design zip file in the following path : ???
2. Unzip the test board zip file
3. Copy the HSS folder (hart-software-services-<HSS version>) from softconsole_source folder in the SoftConsole workspace folder
4. Open SoftConsole software as administrator
5. Select correct directory as workspace directory. The workspace folder must consist of hart-software-services-<HSS version> folder.
6. Left click on board folder
   
7. There is created already a subfolder for TEM0007 module and HSS is ready to be compiled as shown:
   
   TEM0007 HSS

   

8. Right click on hart-software-services-<HSS version> and click on Build project to compile it.
9. It is ready to program created hex file  on the Polarfire SoC. See Programming

Note that HSS can be changed for every TEM0007 variant. Therefore the hex file for every variant  is created  and saved in the following path of test design folder separately: (prebuilt/soctware/<short name of the module variant>)

Creating XML file in PolarfireSoC MSS Configurator Software

To create HSS file for a desired module variant the saved MSS configuration xml file in soc_fpgs_design/xml/ folder must be matched for its related xml file. To do it:

1. Open the PolarfireSoC MSS  Configurator  software.
2. Click on Project→Open
3. Select the generated TEM0007_MSS.cfg file that is saved in the libero_source/mss folder while creating the Libero design.
4. Click on Generate icon. It will be opened a window to enter the desired path for generated xml file.
   
   Creating xml file

   

5. MSS configuration xml file is generated. This file must be imported in SoftConsole software. To import this file copy the generated MSS configuration xml file and replace it with previous xml file in the following path ( <softconsole workspace folder>/ hart-software-services-<HSS version>/boards/TEM0007/soc_fpga_design/xml ).
6. In SoftConsole software click on Project/Clean.
7. In SoftConsole software delete all configuration header files in hart-software-services-<HSS version>/boards/TEM0007/fpga_design-config folder.
   
   Delete configuration header files

   

   
   
8. In SoftConsole software compile HSS again by clicking on Project/Build Project.
9. The new configuration header files will be generated again by the python script in hart-software-services-<HSS version>/tools/polarfire-soc-configuration-generator/mpfs_configuration_generator.py folder. The generated hex file can be found in the hart-software-services-<HSS version>/Default folder.
10. This new hex file must be replaced in Libero to generate new Bitstream file, if this hex file should be attached in Bitstream file. See Libero SoC
    Note that this hex file can be programmed in eNVM in SoftConsole directly.

Libero SoC

Trenz Electronic provides a tcl based built environment based on Libero Design Flow.

See also:

• Project Delivery - Microchip devices

The most Trenz Electronic FPGA Reference Designs are TCL-script based projects.

The "normal" Libero project will be generated in the subfolder "/Libero/" and the additional software part will be generated in the subfolder "/software/" after executing scripts.

To create project do the following steps:

1. Execute "Generate_TEM0007_Hardware-Design_in_Libero_SoC_v2023.1.cmd"
2. Choose one of the following options::
   1. Press 0 , if the path of installed libero software is : C:/Microchip/Libero_SoC_v2023.1/Designer/bin/libero.exe 
      
   2. Press 1, if it will be entered the path  Microchip or Libero SoC installations folder. The script selects automatically the Libero exe.
   3. Press 2, if it will be entered the full path to the Libero SoC exe.
      
   4. Press 3 to exit the script.
3. Select your board in "Board selection" , if there is more than one variant.
4. Choose one of the following options for prefered hardware description language:
   1. Option 0 : VHDL
   2. Option 1 : VERILOG
   3. Option 2 :  To exit th script
5. If the suggested name for the project is acceptable enter y or t or 1. Otherwise enter n or f or 0 and enter the desired name.
6.  Project will be generated automatically.
7. Open the generated project by entering y or t or 1
   

   

   Example
8. After opening Libero project double click on Generate Bitstream menu in Design Flow box to generate the bitstream file.
   
   Generate Bitstream

   

   
   
9. After generating bit stream file double click on Configure Design Initialization Data and Memories in Design Flow bow. It will be opened a window.
   
   Configure Memory

   

10. Click on eNVM and after that on Add and click on Add Boot Mode 1 Client.
    
11. Enter the path of generated *.hex File by SoftConsole software (HSS) and click on OK.
    
    HSS generated *.hex File attachment

    

12. Save the project and double click on Generate Bitstream again.
    
    Generate Bitstream again

    

13. Double click on Flashpro Express to generate *.job File
    
    Generate Job File

    

Launch

Hardware Setup

see Modified TE0703 for Microchip Getting Started

Programming

Programming eNVM

The eNVM is a user non-volatile flash memory that can be programmed independently. There is two methods to program eNVM:

Programming eNVM in SoftConsole

To program HSS *.elf file on FPGA:

• Prepare the hardware see Hardware Setup
• Open SoftConsole software as administrator, if it is not done yet.
• Select correct directory as workspace directory.
• Build the hart-software-services-master , if it is not done yet.
• Click on Run > External Tools > Polarfire SoC program non-secure boot-mode 1

Programming eNVM in Flashpro Express

The HSS generated hex file can be attached to bitstream file. For more information see Design Flow

To program the eNVM in Flashpro Express see #Using FlashPro Express

Programming Bitstream

There is two ways to program bitstream file on FPGA:

• Using Libero SoC

  • Connect the TEM0703 board via its Mini-USB connector. (J4)
  • After generating bitstream in Libero click on  Run PROGRAM Action to program bitstream file on FPGA.
    
    Programming FPGA using Libero SoC

    

• Using FPExpress software

  • Connect the board via USB connector
  • Export  *.job file , if does not exist yet.
    
    Job File Exporting using Libero SoC

    

  • Open FPExpress software

    

    
    

  • Click on new
  • Give path of job file by clicking on Browse
  • Click on OK
  • Click on RUN

Get prebuilt boot binaries

1. Run create_project_win.cmd/create_project_linux.sh
2. Select Module in 'Board selection'
3. Click on 'Export prebuilt files' button
   1. Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened

SD-Boot mode

This module supports SD card boot mode. There is no dip switch to select boot mode. The selection between SD card or other boot mode will be done in HSS. TEM0007 module supports SD card boot mode and JTAG boot mode.

Prepare SD card as follows for SD card boot mode:

1. Extract SD_Card.zip file
2. Now there is a image file (SD_Card.img)
3. Alternative SD card can be written via Win32DiskImager or balenaEtcher softwares in Windows OS.
4. In the case of writing image file in  linux there are two commands to write image file on the SD card after mounting SD card in the host linux same as WSL:

1. 1. Insert SD card in the SD card reader
   2. bmaptool command

      bmaptool copy --nobmap <Path of image file *.img>  /dev/sdX

      
      
      1. After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.
   3. dd command

      dd if=<Path of image file *.img> of=/dev/sdX

      1. After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.

JTAG

Not used on this example.

Usage

1. Prepare HW like described on section Hardware Setup
2. Connect UART USB (most cases same as JTAG)
3. Connect your board to the network
4. Power on PCB

UART

1. Open two serial console for HSS and Linux console (e.g. PuTTY)

   1. Select COM Port of linux console (UART1)

      Win OS: see device manager

      Linux OS: see  dmesg | grep tty  (UART is *USB1)

   2. Select COM port if HSS console (UART0)
   3. Speed for both consoles : 115200
2. Press reset button
3. Console output depends on used Software project, see Software Design - SDK#Application
4. Linux Console (UART1):

   1. Login data:

      Note: Wait until Linux boot finished

      tem0007 login: root
      

   2. You can use Linux shell now.

      i2cdetect -l        (check I2C Bus)
      ifconfig -a         (ETH0 check)
      lsusb               (USB check)

      Linux Console

      

5. HSS console (UART0):
   
   1. This console can be monitored by user , to know some additional information same as SD card status ( If SD card by booting is detected or not) , U54 cores status or memory size , ....
       
      HSS Console

      

   2. 
      

System Design - Libero

Block Design

The block designs may differ depending on the assembly variant.

HPS Interfaces

Activated interfaces:

Software Design - SoftConsole

Application

Template location: <project folder>/softconsole_source/

Creating new HSS workspace in SoftConsole for neu module variant

• Download the HSS folder here: hart-software-services
• Unzip the hart-software-services-2023.02 zip file in the SoftConsole workspace
• Open SoftConsole software as administrator
• Select correct directory as workspace directory. The workspace folder must consist of hart-software-services-2023.02 folder
• Right click on board folder in the left side and click on new folder
• Rename the folder for desired board. For example for TEM0007 module rename it to TEM0007. If there is TEM0007, this HSS workspace was created already and HSS is ready to be compiled.
  
• Create other subfolders as shown (For example for TEM0007):
  
  
  HSS Structure Example

  

  • hart-software-serevices-2023.02
    • board
      • TEM0007
        • drivers_config
          • fpga_ip
            • miv_ihc
              • Copy miv_ihc_add_mapping.h and miv_ihc_config.h files from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste in this folder.
        • fpga_design_config
          • This folder should be left empty. After compiling the neccessary header files for ddr, clock, IOs and other properties of desired module and hardware design will be generated and saved in this folder by mpfs_configuration_generator.py python script. The python script is saved already in the tools/polarfire-soc-configuration-generator folder.
            
        • mpfs_hal_config
          • Copy  mss_sw_config.h file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste
            
        • soc_fpga_design
          • xml
            • Copy the generated xml with PolarFireSoC MSS Configurator software here. For example TEM0007_MSS_mss_cfg.xml
              
        • Copy the following files from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste in this folder (TEM0007 folder) :
          • hss_board_init.c
            • Edit the following line to avoid using USB interface without DMA. If this line don't be commented, DMA option for USB interface in linux kernel must be deactivated for USB interface to operate USB interface correctly.
              
              hss_board_init.c

              

          • hss_usrt_init.c
          • usrt_helper.c
          • hss_I2Scratch.lds
          • Kconfig
            • Edit Kconfig for example for TEM0007 module as shown:
              
              Kconfig

              Kconfig

              menu "TEM0007 Design Configuration Options"
              
              config SOC_FPGA_DESIGN_XML
              	string "Enter path to Libero XML file"
              	default "boards/$(BOARD)/soc_fpga_design/xml/TEM0007_MSS_mss_cfg.xml"
              	help
              		This option specifies the design XML file to use.
              endmenu
              
              

• • • • • • Makefile
            • Edit Makefile for example for TEM0007 module as shown:
              
              Makefile of TEM0007 folder

              

              Makefile of TEM0007 folder
    • To operate SD card correctly edit the file in the following path: ....\hart-software-services-2023.02\baremetal\polarfire-soc-bare-metal-library\src\platform\drivers\mss\mss_mmc\mss_mmc.c . For last version of hart-software-sevices (Version 2023.06) this bug is fixed.  For more information refer to : https://github.com/polarfire-soc/hart-software-services/commit/b3c277c69cba09b66449b99e8716cd82add8a876
      • Add the delay function mmc_delay(MASK_8BIT);  in the line 787 of mss_mmc.c file:
        
        mss_mmc.c

        
        

        
        

        
        
  • Edit Makefile in hart-software-services-2023.02 Folder for example for TEM0007 as shown:
    
    Makefile of hart-software-services

    

    Makefile of hart-software-services-master folder
  • Copy def_config file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste it in hart-software-services-master folder and rename it to .config file.
    • Edit .config file according to your module. For example for TEM0007 is edited this file as shown:
      
      .config File

      
      #
      # Board/Design Configuration Options
      #
      
      #
      # TEM0007 Trenz electronic GmbH polarfire SoC module Design Configuration Options
      #
      CONFIG_SOC_FPGA_DESIGN_XML="boards/TEM0007/soc_fpga_design/xml/TEM0007_MSS_mss_cfg.xml"
      # end of TEM0007 Design Configuration Options
      # end of Board/Design Configuration Options 
      
      #
      # Services
      #
      CONFIG_SERVICE_BEU=y
      CONFIG_SERVICE_BOOT=y
      
      #
      # Boot Service
      #
      # CONFIG_SERVICE_BOOT_USE_PAYLOAD is not set
      # CONFIG_SERVICE_BOOT_CUSTOM_FLOW is not set
      CONFIG_SERVICE_BOOT_DDR_TARGET_ADDR=0x8e000000
      CONFIG_SERVICE_BOOT_MMC_USE_GPT=y
      # end of Boot Service
      
      CONFIG_SERVICE_DDR=y
      CONFIG_SERVICE_GOTO=y
      CONFIG_SERVICE_IPI_POLL=y
      CONFIG_SERVICE_MMC=y
      
      #
      # MMC
      #
      
      #
      # MMC Mode
      #
      # CONFIG_SERVICE_MMC_MODE_EMMC is not set
      CONFIG_SERVICE_MMC_MODE_SDCARD=y
      # end of MMC Mode
      
      #
      # MMC Voltage
      #
      # CONFIG_SERVICE_MMC_BUS_VOLTAGE_1V8 is not set
      # end of MMC Voltage
      
      #
      # SDIO Control
      #
      CONFIG_SERVICE_MMC_FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT=y
      CONFIG_SERVICE_MMC_FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS=0x4fffff00
      # end of SDIO Control
      
      CONFIG_SERVICE_MMC_SPIN_TIMEOUT=y
      # CONFIG_SERVICE_MMC_SPIN_TIMEOUT_ASSERT is not set
      CONFIG_SERVICE_MMC_SPIN_TIMEOUT_MAX_SPINS=1000000
      # end of MMC
      
      CONFIG_SERVICE_OPENSBI=y
      CONFIG_SERVICE_OPENSBI_IHC=y
      CONFIG_SERVICE_OPENSBI_RPROC=y
      # CONFIG_SERVICE_POWERMODE is not set
      # CONFIG_SERVICE_QSPI is not set
      CONFIG_SERVICE_SCRUB=y
      
      #
      # RAM Scrubbing Service
      #
      CONFIG_SERVICE_SCRUB_MAX_SIZE_PER_LOOP_ITER=4096
      CONFIG_SERVICE_SCRUB_RUN_EVERY_X_SUPERLOOPS=256
      # CONFIG_SERVICE_SCRUB_CACHED_DDR is not set
      # end of RAM Scrubbing Service
      
      CONFIG_SERVICE_SGDMA=y
      # CONFIG_SERVICE_SPI is not set
      CONFIG_SERVICE_TINYCLI=y
      
      #
      # Tiny Command Line Interface
      #
      CONFIG_SERVICE_TINYCLI_TIMEOUT=1
      CONFIG_SERVICE_TINYCLI_REGISTER=y
      # CONFIG_SERVICE_TINYCLI_MONITOR is not set
      # CONFIG_SERVICE_TINYCLI_ENABLE_PREBOOT_TIMEOUT is not set
      # end of Tiny Command Line Interface
      
      # CONFIG_SERVICE_UART is not set
      CONFIG_SERVICE_USBDMSC=y
      
      #
      # USB Device Mass Storage Class
      #
      CONFIG_SERVICE_USBDMSC_REGISTER=y
      # CONFIG_SERVICE_USBDMSC_ENABLE_MAX_SESSION_TIMEOUT is not set
      # end of USB Device Mass Storage Class
      
      CONFIG_SERVICE_WDOG=y
      
      #
      # Watchdog Service
      #
      # CONFIG_SERVICE_WDOG_DEBUG is not set
      CONFIG_SERVICE_WDOG_DEBUG_TIMEOUT_SEC=240
      CONFIG_SERVICE_WDOG_ENABLE_E51=y
      # end of Watchdog Service
      
      # CONFIG_SERVICE_YMODEM is not set
      # end of Services
      
      #
      # General Configuration Options
      #
      
      #
      # Miscellaneous
      #
      #CONFIG_USE_PCIE=y
      CONFIG_USE_PCIE=n
      CONFIG_OPENSBI=y
      CONFIG_USE_IHC=y
      
      #
      # Tamper
      #
      # CONFIG_USE_TAMPER is not set
      # end of Tamper
      
      CONFIG_ALLOW_COLDREBOOT=y
      
      #
      # Cold Reboot
      #
      CONFIG_ALLOW_COLDREBOOT_ALWAYS=y
      # CONFIG_ALLOW_COLDREBOOT_ON_OPENSBI_FAULT is not set
      # end of Cold Reboot
      # end of Miscellaneous
      
      #
      # OpenSBI
      #
      # CONFIG_PROVIDE_DTB is not set
      # end of OpenSBI
      
      #
      # Memory Options
      #
      # CONFIG_SKIP_DDR is not set
      # CONFIG_MEMTEST is not set
      # CONFIG_USE_PDMA is not set
      # CONFIG_INITIALIZE_MEMORIES is not set
      # end of Memory Options
      # end of General Configuration Options
      
      #
      # Build Options
      #
      CONFIG_COLOR_OUTPUT=y
      CONFIG_USE_LOGO=y
      
      #
      # Logo
      #
      CONFIG_LOGO_INVERT_COLORS=y
      # end of Logo
      
      # CONFIG_CC_STACKPROTECTOR_STRONG is not set
      # CONFIG_CC_DUMP_STACKSIZE is not set
      # CONFIG_LD_RELAX is not set
      CONFIG_CC_USE_MAKEDEP=y
      CONFIG_CC_USE_GNU_BUILD_ID=y
      CONFIG_CC_HAS_INTTYPES=y
      CONFIG_DISPLAY_TOOL_VERSIONS=y
      # CONFIG_LOG_FUNCTION_NAMES is not set
      # end of Build Options
      
      #
      # Compression
      #
      CONFIG_COMPRESSION=y
      CONFIG_COMPRESSION_MINIZ=y
      # end of Compression
      
      #
      # Crypto
      #
      # CONFIG_CRYPTO_SIGNING is not set
      # end of Crypto
      
      #
      # Debug Options
      #
      CONFIG_DEBUG_LOG_STATE_TRANSITIONS=y
      CONFIG_DEBUG_LOOP_TIMES=y
      CONFIG_DEBUG_LOOP_TIMES_THRESHOLD=2500000
      # CONFIG_DEBUG_IPI_STATS is not set
      # CONFIG_DEBUG_CHUNK_DOWNLOADS is not set
      # CONFIG_DEBUG_MSCGEN_IPI is not set
      # CONFIG_DEBUG_PROFILING_SUPPORT is not set
      CONFIG_DEBUG_PERF_CTRS=y
      CONFIG_DEBUG_PERF_CTRS_NUM=16
      # CONFIG_DEBUG_RESET_REASON is not set
      # end of Debug Options
      
      #
      # SSMB Options
      #
      # CONFIG_HSS_USE_IHC is not set
      CONFIG_IPI_MAX_NUM_QUEUE_MESSAGES=8
      # CONFIG_IPI_FIXED_BASE is not set
      # end of SSMB Options
      
      

  • Now HSS workspace is ready to be compiled. Right click on hart-software-services-2023.02 and  click on Build Project.
  • After compiling a config.h will be generated in the hart-software-services-2023.02 folder. By opening this header file it can be seen all configurations of .config file.

Software Design - Yocto

Trenz electronic has developed his own BSP for Microchip devices same as polarfire soc in Yocto. In the following will be explained the folders in detail.

In the following table exists more information about required packets and supported version.

Trenz BSP contains of a shell script. If this shell script in be executed , all required processes for making a linux image file will be executed automatically. The user needs only to write the image file on the SD card. To prepare the image file :

1. Download and save meta-trenz-polarefile-bsp folder in the host linux and execute its shell script as shown:
   
   Execute shell script

   	. ./meta-trenz-polarfire-bsp/trenz_polarfire_setup.sh

   
   
2. After compiling image file *.img and its converted zip file *.zip will be saved in trenz bsp folder:

• • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.img
  • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.zip

U-Boot

File location: meta-trenz-<SoC name>-bsp/recipes-bsp/u-boot/

Changes:

• CONFIG_PHY_MARVELL=y

• CONFIG_DEFAULT_DEVICE_TREE="tem0007"

• CONFIG_DEFAULT_FDT_FILE="tem0007.dtb"

• CONFIG_OF_LIST="tem0007"

• CONFIG_DM_GPIO=y

• CONFIG_CMD_GPIO=y

• CONFIG_LOG=y

• CONFIG_LOG_MAX_LEVEL=y

• CONFIG_LOG_CONSOLE=y

• CONFIG_NVMEM=y  → to be able to read MAC vom EEPROM

• CONFIG_DM_RTC=y

Device Tree

U-boot Device Tree

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2020 Microchip Technology Inc.
 * Padmarao Begari <padmarao.begari@microchip.com>
 */

/ {
	aliases {
		cpu1 = &cpu1;
		cpu2 = &cpu2;
		cpu3 = &cpu3;
		cpu4 = &cpu4;
	};
};

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 Microchip Technology Inc.
 * Padmarao Begari <padmarao.begari@microchip.com>
 */

/dts-v1/;

#include "microchip-mpfs.dtsi"
#include "dt-bindings/gpio/gpio.h"

/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ		1000000

/ {
	model = "Microchip PolarFire-SoC Icicle Kit";
	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";

	aliases {
		serial1 = &uart1;
		ethernet0 = &mac0;
		spi0 = &qspi;
	};

	chosen {
		stdout-path = "serial1";
	};

	cpus {
		timebase-frequency = <RTCCLK_FREQ>;
	};

	ddrc_cache: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		clocks = <&clkcfg CLK_DDRC>;
		status = "okay";
	};
   
    usb_phy: usb_phy {
        #phy-cells = <0>;
        compatible = "usb-nop-xceiv";
        reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
        reset-names = "OTG_RST";
    };    
};

&uart1 {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-mmc-highspeed;
	cap-sd-highspeed;
    cd-debounce-delay-ms;
	card-detect-delay = <200>;
	// mmc-ddr-1_8v;
	// mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&i2c1 {
	status = "okay";
    #address-cells = <1>;
	#size-cells = <0>;
	eeprom: eeprom@50 {
		compatible = "microchip,24aa025", "atmel,24c02";
        //compatible = "atmel,24c02";
		reg = <0x50>;
		#address-cells = <1>;
		#size-cells = <1>;        
		eth0_addr: eth-mac-addr@FA {
			reg = <0xFA 0x06>;
		};
	};
};

&refclk {
	clock-frequency = <125000000>;
};

&mac1 {
	status = "disabled";
};

&mac0 {
	status = "okay";
	phy-mode = "sgmii";
    nvmem-cells = <&eth0_addr>;
	nvmem-cell-names = "mac-address";
	phy-handle = <&phy0>;
	phy0: ethernet-phy@1 {
		device-type = "ethernet-phy";
		reg = <1>;       
        reset-names = "ETH_RST";
        reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};
};



&qspi {
	status = "okay";
	num-cs = <1>;
	flash0: spi-nor@0 {
		compatible = "spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <20000000>;
		spi-cpol;
		spi-cpha;
	};
};

&usb {
	status = "okay";
	dr_mode = "otg";  
	// dr_mode = "host";
	phys = <&usb_phy>;
};

Kernel Device Tree

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */

/dts-v1/;

#include "mpfs.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ		1000000

/ {
	#address-cells = <2>;
	#size-cells = <2>;

    
	model = "Trenz TEM0007";
	compatible = "trenz,tem0007","microchip,mpfs";
    
	aliases {
		ethernet0 = &mac0;
		serial0 = &mmuart0;
		serial1 = &mmuart1;
		serial2 = &mmuart2;
		serial3 = &mmuart3;
		serial4 = &mmuart4;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};

	cpus {
		timebase-frequency = <MTIMER_FREQ>;
	};



	//******************************************************//

	ddrc_cache: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		status = "okay";
	};

	reserved-memory {	
		#address-cells = <2>;
		#size-cells = <2>;

		ranges;

		fabricbuf0ddrc: buffer@A0000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xA0000000 0x0 0x2000000>;
			no-map;
		};
	};
    
	udmabuf0 {
		compatible = "ikwzm,u-dma-buf";
		device-name = "udmabuf-ddr-c0";
		minor-number = <0>;
		size = <0x0 0x2000000>;
		memory-region = <&fabricbuf0ddrc>;
		sync-mode = <3>;
	};


	//******************************************************//

	usb_phy: usb_phy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
		reset-names = "OTG_RST";
	};


	soc {
		dma-ranges = <0 0 0 0 0x40 0>;
	};
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	interrupts = <53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>,
		<53>, <53>, <53>, <53>;
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";    
	#address-cells = <1>;
	#size-cells = <0>;

	eeprom: eeprom@50 {
		compatible = "microchip,24aa025", "atmel,24c02";
        //compatible = "atmel,24c02";
		reg = <0x50>;
		#address-cells = <1>;
		#size-cells = <1>;        
		eth0_addr: eth-mac-addr@FA {
			reg = <0xFA 0x06>;
		};
	};
};


&mac0 {
	status = "okay";
	phy-mode = "sgmii";    
	nvmem-cells = <&eth0_addr>;
	nvmem-cell-names = "mac-address";
                                   
	phy-handle = <&phy0>;
	phy0: ethernet-phy@1 {
		device-type = "ethernet-phy";
		reg = <1>;
		reset-names = "ETH_RST";
		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};
};

&mbox {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	// mmc-ddr-1_8v;
	// mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};


&mmuart1 {
	status = "okay";
};

&mmuart2 {
	status = "okay";
};

&mmuart3 {
	status = "okay";
};

&mmuart4 {
	status = "okay";
};


&qspi {
	status = "okay";
	num-cs = <1>;
};

&refclk {
	clock-frequency = <125000000>;
};


&spi0 {
	status = "okay";
};


&usb {
	status = "okay";
	dr_mode = "otg";  
	// dr_mode = "host";
	phys = <&usb_phy>;
};

&syscontroller {
    status = "okay";
};
    

Kernel

File location: meta-trenz-<SoC name>-bsp/recipes-kernel/linux/

Changes:

• CONFIG_CMDLINE_BOOL=y

• CONFIG_CMDLINE="earlycon=sbi root=/dev/mmcblk0p3 rootwait uio_pdrv_genirq.of_id=generic-uio"

• CONFIG_EEPROM_AT24=y

• CONFIG_NVMEM=y

• CONFIG_NVMEM_SYS=y

• CONFIG_REGMAP_I2C=y

• CONFIG_MARVELL_PHY=y

• CONFIG_LEDS_GPIO=y

• CONFIG_LEDS_CLASS=y

• CONFIG_NEW_LEDS=y

• CONFIG_GPIOLIB=y

• CONFIG_USB_MUSB_HOST=y

• CONFIG_USB_MUSB_DUAL_ROLE=y

• CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n

• CONFIG_MTD_UBI=y

• CONFIG_MTD_CMDLINE_PARTS=y

• CONFIG_UBIFS_FS=y

• CONFIG_MTD_SPI_NOR=y

• CONFIG_OF_OVERLAY=y

• CONFIG_OF_CONFIGFS=y

• CONFIG_MFD_SENSEHAT_CORE=m

• CONFIG_INPUT_JOYDEV=m

• CONFIG_INPUT_JOYSTICK=y

• CONFIG_JOYSTICK_SENSEHAT=m

• CONFIG_AUXDISPLAY=y

• CONFIG_SENSEHAT_DISPLAY=m

• CONFIG_HTS221=m

• CONFIG_IIO_ST_PRESS=m

• CONFIG_IIO_ST_LSM6DSX=m

• CONFIG_IIO_ST_MAGN_3AXIS=m

• #CONFIG_MUSB_PIO_ONLY is not set

• CONFIG_USB_INVENTRA_DMA=y

Images

Image recipe for minimal console image

File location: meta-trenz-<SoC name>-bsp/recipes-core/images/

Image recipes:

• te-image-minimal.bb: create minimal linux image

Added packages/recipes:

• startup

• iputils-ping

• expect

• rsync

• rng-tools

• iperf3

• devmem2

• can-utils

• usbutils

• pciutils

• polarfire-soc-linux-examples

• dt-overlay-mchp

• libgpiod

• libgpiod-tools

• libgpiod-dev

• i2c-tools

• vim vim-vimrc

• net-tools

• htop

• iw

• python3

• python3-pip

• python3-flask

• python3-flask-dev

• python3-werkzeug

• libudev

• glib-2.0

• sqlite3

• dtc

• cmake

• tar

• wget

• zip

• mtd-utils

• mtd-utils-ubifs

  
  

Rootfs

Used filesystem: Root file system (RootFS)

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