This is preliminary based on Vivado 2015.4 release, the "DDR Less" flow should become even easier with the next Vivado releases.
Step by Step
- In Vivado IPI create a BD and configure PS7 block with no DDR, one UART should be enabled also
- in SDK create FSBL, in main.c add one line, and comment out one line
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0
#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
//Status = DDRInitCheck();
Create BOOT.BIN
Thats all, PS will load the FPGA bitstream and then do nothing.
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