Table of Contents
Overview
The Trenz Electronic TE0714 is an industrial-grade SoM (System om Module) based on Xilinx Artix-7, 16 megabyte Flash memory and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.
Block diagram
Board Components
 |  |
Top view | Bottom view |
Main Components:
Artix-7
B2B-Connector
JM1
JM2
Key Features
Xilinx Artix-7 (A15T, A35T, A50T)
- Rugged for shock and high vibration
- 16 MByte QSPI Flash memory
- Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
- 144 FPGA I/Os (68 LVDS pairs possible, Analog 1 x ADC) available on board-to-board connectors
- 4 GTP (high-performance transceiver) lanes
- GTP (high-performance transceiver) clock input
- On-board high-efficiency DC-DC converters
- 3 A x 1.35 V power rail
- 3 A x 1 V power rail
- 1.5 A x 1 V power rail
- 1.5 A x 1.2 V power rail
- 600 mA x 1.8 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- LED
- Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request. Possible options:
- FPGA Type (A15T, A35T, A50T), temperature grade
- GT Clock Frequency (or none if not assembled)
- PL Clock Frequency and precision or none if not assembled)
- Config and B14 Bank Voltage: 1.8V or 3.3V
- SPI Flash type (or none if not assembled)
- LED Color (or none if not assembled)
- PUDC Pin strapping (pull high or pull down)
- GT Power Enable pin strapping (default power enabled or disabled)
Current Assembly Variants
| Variant | FPGA | GT Clock | PL Clock | PUDC | GT PWR Enable | B14/Config Voltage | SPI Flash | LED |
|---|---|---|---|---|---|---|---|---|
| Standard | A35T-2I | 125MHz | 25Mhz | HIGH | Enabled | 3.3V | S25FL127S | Red |
| 35-2IC6 | A35T-2I | 125MHz | 25MHz | HIGH | Enabled | 1.8V | N25Q128 | Red |
Signals, Interfaces and Pins
Boot Modes
Two boot modes are controlled by the MODE signal on the board to board (B2B) connector:
MODE signal | Boot Mode |
|---|---|
high or open | Master SPI |
low or ground | Slave SelectMAP |
JTAG
JTAG access to the Xilinx Artix-7 device is provided through connector JM1.
Signal | B2B Pin |
|---|---|
| TCK | JM1: 89 |
| TDI | JM1: 85 |
| TDO | JM1: 87 |
| TMS | JM1: 91 |
Clocking
Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
| CLK | 25 MHz | U8, SiT8008 |
| |
| MGT_CLK |
|
|
|
|
Peripherals
LED's
There is 1 LED on TE0714:
LED | Color | Connected to | Notes |
|---|---|---|---|
D4 | green | pin K18 |
|
Power
For startup, a power supply with minimum current capability of 1A is recommended.
Power Supplies
Vin | 3.3 V | Typical 200 mA, depending on customer design and connections |
Bank Voltages
Bank | Voltage | Notes |
|---|---|---|
0 Config and B14 | 1.8V or 3.3V | Depends on assembly option |
15 | User | Has to be supplied from base, max 3.3V |
34 | User | Has to be supplied from base, max 3.3V |
Initial Delivery state
Storage device name | Content | Notes |
|---|---|---|
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed |
Hardware Revision History
| Revision | Changes |
|---|---|
01 | Current Hardware Revision, no changes |
Technical Specification
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes | Reference document |
|---|---|---|---|---|---|
Vin supply voltage | -0.1 | 6.3 | V | ||
| PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | Xilinx document DS181 | |
| I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | Xilinx document DS181 | |
| GT Receiver (RXP/RXN) and Transmitter (TXP/TXN) | -0.5 | 1.26 | V | Xilinx document DS181 | |
Voltage on Module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal | Xilinx document DS181 |
Storage Temperature | -40 | +85 | C | ||
Storage Temperature without the LXDC2HL18A-052 | -40 | +125 | C |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Notes | Reference document |
|---|---|---|---|---|---|
| Vin supply voltage | 3.135 | 5.5 | V | ||
| IO Bank supply voltage for I/O banks | 1.14 | 3.465 | V | Xilinx document DS181 | |
| I/O input voltage for HR I/O banks | -0.20 | Vcco + 0.20 | V | Xilinx document DS181 | |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | For assembly variant with 3.3V on config banks | Xilinx document DS181 |
Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Artix-7 device (DS181).
Physical Dimensions
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm and can be found here.
Temperature Ranges
Commercial grade modules
All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weight
| Variant | Weight g | Note |
|---|---|---|
| 2IC6 | 8.3 | Plain Module |
Document Change History
Date | Revision | Authors | Description |
|---|---|---|---|
2016-06-01 | initial version |
Disclaimer
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